1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek T-PHY Controller Device Tree Bindings 9 10maintainers: 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 12 13description: | 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- 20 Version 1: 21 port offset bank 22 shared 0x0000 SPLLC 23 0x0100 FMREG 24 u2 port0 0x0800 U2PHY_COM 25 u3 port0 0x0900 U3PHYD 26 0x0a00 U3PHYD_BANK2 27 0x0b00 U3PHYA 28 0x0c00 U3PHYA_DA 29 u2 port1 0x1000 U2PHY_COM 30 u3 port1 0x1100 U3PHYD 31 0x1200 U3PHYD_BANK2 32 0x1300 U3PHYA 33 0x1400 U3PHYA_DA 34 u2 port2 0x1800 U2PHY_COM 35 ... 36 37 Version 2/3: 38 port offset bank 39 u2 port0 0x0000 MISC 40 0x0100 FMREG 41 0x0300 U2PHY_COM 42 u3 port0 0x0700 SPLLC 43 0x0800 CHIP 44 0x0900 U3PHYD 45 0x0a00 U3PHYD_BANK2 46 0x0b00 U3PHYA 47 0x0c00 U3PHYA_DA 48 u2 port1 0x1000 MISC 49 0x1100 FMREG 50 0x1300 U2PHY_COM 51 u3 port1 0x1700 SPLLC 52 0x1800 CHIP 53 0x1900 U3PHYD 54 0x1a00 U3PHYD_BANK2 55 0x1b00 U3PHYA 56 0x1c00 U3PHYA_DA 57 u2 port2 0x2000 MISC 58 ... 59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back 61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are 62 added on V2; the FMREG bank for slew rate calibration is not used anymore 63 and reserved on V3; 64 65properties: 66 $nodename: 67 pattern: "^t-phy@[0-9a-f]+$" 68 69 compatible: 70 oneOf: 71 - items: 72 - enum: 73 - mediatek,mt2701-tphy 74 - mediatek,mt7623-tphy 75 - mediatek,mt7622-tphy 76 - mediatek,mt8516-tphy 77 - const: mediatek,generic-tphy-v1 78 - items: 79 - enum: 80 - mediatek,mt2712-tphy 81 - mediatek,mt7629-tphy 82 - mediatek,mt8183-tphy 83 - mediatek,mt8186-tphy 84 - mediatek,mt8192-tphy 85 - mediatek,mt8365-tphy 86 - const: mediatek,generic-tphy-v2 87 - items: 88 - enum: 89 - mediatek,mt8188-tphy 90 - mediatek,mt8195-tphy 91 - const: mediatek,generic-tphy-v3 92 - const: mediatek,mt2701-u3phy 93 deprecated: true 94 - const: mediatek,mt2712-u3phy 95 deprecated: true 96 - const: mediatek,mt8173-u3phy 97 98 reg: 99 description: 100 Register shared by multiple ports, exclude port's private register. 101 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for 102 T-PHY V2/V3, such as mt2712. 103 maxItems: 1 104 105 "#address-cells": 106 enum: [1, 2] 107 108 "#size-cells": 109 enum: [1, 2] 110 111 # Used with non-empty value if optional 'reg' is not provided. 112 # The format of the value is an arbitrary number of triplets of 113 # (child-bus-address, parent-bus-address, length). 114 ranges: true 115 116 mediatek,src-ref-clk-mhz: 117 description: 118 Frequency of reference clock for slew rate calibrate 119 default: 26 120 121 mediatek,src-coef: 122 description: 123 Coefficient for slew rate calibrate, depends on SoC process 124 $ref: /schemas/types.yaml#/definitions/uint32 125 default: 28 126 127# Required child node: 128patternProperties: 129 "^(usb|pcie|sata)-phy@[0-9a-f]+$": 130 type: object 131 description: 132 A sub-node is required for each port the controller provides. 133 Address range information including the usual 'reg' property 134 is used inside these nodes to describe the controller's topology. 135 136 properties: 137 reg: 138 maxItems: 1 139 140 clocks: 141 minItems: 1 142 items: 143 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 144 - description: Reference clock of analog phy 145 description: 146 Uses both clocks if the clock of analog and digital phys are 147 separated, otherwise uses "ref" clock only if needed. 148 149 clock-names: 150 minItems: 1 151 items: 152 - const: ref 153 - const: da_ref 154 155 "#phy-cells": 156 const: 1 157 description: | 158 The cells contain the following arguments. 159 160 - description: The PHY type 161 enum: 162 - PHY_TYPE_USB2 163 - PHY_TYPE_USB3 164 - PHY_TYPE_PCIE 165 - PHY_TYPE_SATA 166 167 nvmem-cells: 168 items: 169 - description: internal R efuse for U2 PHY or U3/PCIe PHY 170 - description: rx_imp_sel efuse for U3/PCIe PHY 171 - description: tx_imp_sel efuse for U3/PCIe PHY 172 description: | 173 Phandles to nvmem cell that contains the efuse data; 174 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these 175 three items should be provided at the same time for U3/PCIe PHY, 176 when use software to load efuse; 177 If unspecified, will use hardware auto-load efuse. 178 179 nvmem-cell-names: 180 items: 181 - const: intr 182 - const: rx_imp 183 - const: tx_imp 184 185 # The following optional vendor properties are only for debug or HQA test 186 mediatek,eye-src: 187 description: 188 The value of slew rate calibrate (U2 phy) 189 $ref: /schemas/types.yaml#/definitions/uint32 190 minimum: 1 191 maximum: 7 192 193 mediatek,eye-vrt: 194 description: 195 The selection of VRT reference voltage (U2 phy) 196 $ref: /schemas/types.yaml#/definitions/uint32 197 minimum: 1 198 maximum: 7 199 200 mediatek,eye-term: 201 description: 202 The selection of HS_TX TERM reference voltage (U2 phy) 203 $ref: /schemas/types.yaml#/definitions/uint32 204 minimum: 1 205 maximum: 7 206 207 mediatek,intr: 208 description: 209 The selection of internal resistor (U2 phy) 210 $ref: /schemas/types.yaml#/definitions/uint32 211 minimum: 1 212 maximum: 31 213 214 mediatek,discth: 215 description: 216 The selection of disconnect threshold (U2 phy) 217 $ref: /schemas/types.yaml#/definitions/uint32 218 minimum: 1 219 maximum: 15 220 221 mediatek,bc12: 222 description: 223 Specify the flag to enable BC1.2 if support it 224 type: boolean 225 226 mediatek,syscon-type: 227 $ref: /schemas/types.yaml#/definitions/phandle-array 228 maxItems: 1 229 description: 230 A phandle to syscon used to access the register of type switch, 231 the field should always be 3 cells long. 232 items: 233 items: 234 - description: 235 The first cell represents a phandle to syscon 236 - description: 237 The second cell represents the register offset 238 - description: 239 The third cell represents the index of config segment 240 enum: [0, 1, 2, 3] 241 242 required: 243 - reg 244 - "#phy-cells" 245 246 additionalProperties: false 247 248required: 249 - compatible 250 - "#address-cells" 251 - "#size-cells" 252 - ranges 253 254additionalProperties: false 255 256examples: 257 - | 258 #include <dt-bindings/clock/mt8173-clk.h> 259 #include <dt-bindings/interrupt-controller/arm-gic.h> 260 #include <dt-bindings/interrupt-controller/irq.h> 261 #include <dt-bindings/phy/phy.h> 262 usb@11271000 { 263 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 264 reg = <0x11271000 0x3000>, <0x11280700 0x0100>; 265 reg-names = "mac", "ippc"; 266 phys = <&u2port0 PHY_TYPE_USB2>, 267 <&u3port0 PHY_TYPE_USB3>, 268 <&u2port1 PHY_TYPE_USB2>; 269 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 270 clocks = <&topckgen CLK_TOP_USB30_SEL>; 271 clock-names = "sys_ck"; 272 }; 273 274 t-phy@11290000 { 275 compatible = "mediatek,mt8173-u3phy"; 276 reg = <0x11290000 0x800>; 277 #address-cells = <1>; 278 #size-cells = <1>; 279 ranges; 280 281 u2port0: usb-phy@11290800 { 282 reg = <0x11290800 0x100>; 283 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; 284 clock-names = "ref", "da_ref"; 285 #phy-cells = <1>; 286 }; 287 288 u3port0: usb-phy@11290900 { 289 reg = <0x11290900 0x700>; 290 clocks = <&clk26m>; 291 clock-names = "ref"; 292 #phy-cells = <1>; 293 }; 294 295 u2port1: usb-phy@11291000 { 296 reg = <0x11291000 0x100>; 297 #phy-cells = <1>; 298 }; 299 }; 300 301... 302