1*f482f76cSDaniel Golle# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*f482f76cSDaniel Golle%YAML 1.2 3*f482f76cSDaniel Golle--- 4*f482f76cSDaniel Golle$id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml# 5*f482f76cSDaniel Golle$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f482f76cSDaniel Golle 7*f482f76cSDaniel Golletitle: MediaTek MT7988 XFI T-PHY 8*f482f76cSDaniel Golle 9*f482f76cSDaniel Gollemaintainers: 10*f482f76cSDaniel Golle - Daniel Golle <daniel@makrotopia.org> 11*f482f76cSDaniel Golle 12*f482f76cSDaniel Golledescription: 13*f482f76cSDaniel Golle The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes 14*f482f76cSDaniel Golle used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in 15*f482f76cSDaniel Golle MediaTek's 10G-capabale MT7988 SoC. 16*f482f76cSDaniel Golle In MediaTek's SDK sources, this unit is referred to as "pextp". 17*f482f76cSDaniel Golle 18*f482f76cSDaniel Golleproperties: 19*f482f76cSDaniel Golle compatible: 20*f482f76cSDaniel Golle const: mediatek,mt7988-xfi-tphy 21*f482f76cSDaniel Golle 22*f482f76cSDaniel Golle reg: 23*f482f76cSDaniel Golle maxItems: 1 24*f482f76cSDaniel Golle 25*f482f76cSDaniel Golle clocks: 26*f482f76cSDaniel Golle items: 27*f482f76cSDaniel Golle - description: XFI PHY clock 28*f482f76cSDaniel Golle - description: XFI register clock 29*f482f76cSDaniel Golle 30*f482f76cSDaniel Golle clock-names: 31*f482f76cSDaniel Golle items: 32*f482f76cSDaniel Golle - const: xfipll 33*f482f76cSDaniel Golle - const: topxtal 34*f482f76cSDaniel Golle 35*f482f76cSDaniel Golle resets: 36*f482f76cSDaniel Golle items: 37*f482f76cSDaniel Golle - description: Reset controller corresponding to the phy instance. 38*f482f76cSDaniel Golle 39*f482f76cSDaniel Golle mediatek,usxgmii-performance-errata: 40*f482f76cSDaniel Golle $ref: /schemas/types.yaml#/definitions/flag 41*f482f76cSDaniel Golle description: 42*f482f76cSDaniel Golle One instance of the T-PHY on MT7988 suffers from a performance 43*f482f76cSDaniel Golle problem in 10GBase-R mode which needs a work-around in the driver. 44*f482f76cSDaniel Golle This flag enables a work-around ajusting an analog phy setting and 45*f482f76cSDaniel Golle is required for XFI Port0 of the MT7988 SoC to be in compliance with 46*f482f76cSDaniel Golle the SFP specification. 47*f482f76cSDaniel Golle 48*f482f76cSDaniel Golle "#phy-cells": 49*f482f76cSDaniel Golle const: 0 50*f482f76cSDaniel Golle 51*f482f76cSDaniel Gollerequired: 52*f482f76cSDaniel Golle - compatible 53*f482f76cSDaniel Golle - reg 54*f482f76cSDaniel Golle - clocks 55*f482f76cSDaniel Golle - clock-names 56*f482f76cSDaniel Golle - resets 57*f482f76cSDaniel Golle - "#phy-cells" 58*f482f76cSDaniel Golle 59*f482f76cSDaniel GolleadditionalProperties: false 60*f482f76cSDaniel Golle 61*f482f76cSDaniel Golleexamples: 62*f482f76cSDaniel Golle - | 63*f482f76cSDaniel Golle #include <dt-bindings/clock/mediatek,mt7988-clk.h> 64*f482f76cSDaniel Golle soc { 65*f482f76cSDaniel Golle #address-cells = <2>; 66*f482f76cSDaniel Golle #size-cells = <2>; 67*f482f76cSDaniel Golle 68*f482f76cSDaniel Golle phy@11f20000 { 69*f482f76cSDaniel Golle compatible = "mediatek,mt7988-xfi-tphy"; 70*f482f76cSDaniel Golle reg = <0 0x11f20000 0 0x10000>; 71*f482f76cSDaniel Golle clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, 72*f482f76cSDaniel Golle <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; 73*f482f76cSDaniel Golle clock-names = "xfipll", "topxtal"; 74*f482f76cSDaniel Golle resets = <&watchdog 14>; 75*f482f76cSDaniel Golle mediatek,usxgmii-performance-errata; 76*f482f76cSDaniel Golle #phy-cells = <0>; 77*f482f76cSDaniel Golle }; 78*f482f76cSDaniel Golle }; 79*f482f76cSDaniel Golle 80*f482f76cSDaniel Golle... 81