xref: /linux/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml (revision ae99fb8baafc881b35aa0b79d7ac0178a7c40c89) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings
8
9maintainers:
10  - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
11
12description: |+
13  Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
14  node is used to reference the base address of eMMC phy registers.
15
16  The eMMC PHY node should be the child of a syscon node with the
17  required property:
18
19  - compatible:         Should be one of the following:
20                        "intel,lgm-syscon", "syscon"
21  - reg:
22      maxItems: 1
23
24properties:
25  compatible:
26      const: intel,lgm-emmc-phy
27
28  "#phy-cells":
29    const: 0
30
31  reg:
32    maxItems: 1
33
34  clocks:
35    maxItems: 1
36
37required:
38  - "#phy-cells"
39  - compatible
40  - reg
41  - clocks
42
43examples:
44  - |
45    sysconf: chiptop@e0200000 {
46      compatible = "intel,lgm-syscon", "syscon";
47      reg = <0xe0200000 0x100>;
48      #address-cells = <1>;
49      #size-cells = <1>;
50
51      emmc_phy: emmc-phy@a8 {
52        compatible = "intel,lgm-emmc-phy";
53        reg = <0x00a8 0x10>;
54        clocks = <&emmc>;
55        #phy-cells = <0>;
56      };
57    };
58...
59