1*5bc99910SRamuthevar Vadivel Murugan# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*5bc99910SRamuthevar Vadivel Murugan%YAML 1.2 3*5bc99910SRamuthevar Vadivel Murugan--- 4*5bc99910SRamuthevar Vadivel Murugan$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# 5*5bc99910SRamuthevar Vadivel Murugan$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5bc99910SRamuthevar Vadivel Murugan 7*5bc99910SRamuthevar Vadivel Murugantitle: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings 8*5bc99910SRamuthevar Vadivel Murugan 9*5bc99910SRamuthevar Vadivel Muruganmaintainers: 10*5bc99910SRamuthevar Vadivel Murugan - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> 11*5bc99910SRamuthevar Vadivel Murugan 12*5bc99910SRamuthevar Vadivel Murugandescription: |+ 13*5bc99910SRamuthevar Vadivel Murugan Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon 14*5bc99910SRamuthevar Vadivel Murugan node is used to reference the base address of eMMC phy registers. 15*5bc99910SRamuthevar Vadivel Murugan 16*5bc99910SRamuthevar Vadivel Murugan The eMMC PHY node should be the child of a syscon node with the 17*5bc99910SRamuthevar Vadivel Murugan required property: 18*5bc99910SRamuthevar Vadivel Murugan 19*5bc99910SRamuthevar Vadivel Murugan - compatible: Should be one of the following: 20*5bc99910SRamuthevar Vadivel Murugan "intel,lgm-syscon", "syscon" 21*5bc99910SRamuthevar Vadivel Murugan - reg: 22*5bc99910SRamuthevar Vadivel Murugan maxItems: 1 23*5bc99910SRamuthevar Vadivel Murugan 24*5bc99910SRamuthevar Vadivel Muruganproperties: 25*5bc99910SRamuthevar Vadivel Murugan compatible: 26*5bc99910SRamuthevar Vadivel Murugan const: intel,lgm-emmc-phy 27*5bc99910SRamuthevar Vadivel Murugan 28*5bc99910SRamuthevar Vadivel Murugan "#phy-cells": 29*5bc99910SRamuthevar Vadivel Murugan const: 0 30*5bc99910SRamuthevar Vadivel Murugan 31*5bc99910SRamuthevar Vadivel Murugan reg: 32*5bc99910SRamuthevar Vadivel Murugan maxItems: 1 33*5bc99910SRamuthevar Vadivel Murugan 34*5bc99910SRamuthevar Vadivel Murugan clocks: 35*5bc99910SRamuthevar Vadivel Murugan maxItems: 1 36*5bc99910SRamuthevar Vadivel Murugan 37*5bc99910SRamuthevar Vadivel Muruganrequired: 38*5bc99910SRamuthevar Vadivel Murugan - "#phy-cells" 39*5bc99910SRamuthevar Vadivel Murugan - compatible 40*5bc99910SRamuthevar Vadivel Murugan - reg 41*5bc99910SRamuthevar Vadivel Murugan - clocks 42*5bc99910SRamuthevar Vadivel Murugan 43*5bc99910SRamuthevar Vadivel Muruganexamples: 44*5bc99910SRamuthevar Vadivel Murugan - | 45*5bc99910SRamuthevar Vadivel Murugan sysconf: chiptop@e0200000 { 46*5bc99910SRamuthevar Vadivel Murugan compatible = "intel,lgm-syscon", "syscon"; 47*5bc99910SRamuthevar Vadivel Murugan reg = <0xe0200000 0x100>; 48*5bc99910SRamuthevar Vadivel Murugan 49*5bc99910SRamuthevar Vadivel Murugan emmc-phy: emmc-phy@a8 { 50*5bc99910SRamuthevar Vadivel Murugan compatible = "intel,lgm-emmc-phy"; 51*5bc99910SRamuthevar Vadivel Murugan reg = <0x00a8 0x10>; 52*5bc99910SRamuthevar Vadivel Murugan clocks = <&emmc>; 53*5bc99910SRamuthevar Vadivel Murugan #phy-cells = <0>; 54*5bc99910SRamuthevar Vadivel Murugan }; 55*5bc99910SRamuthevar Vadivel Murugan }; 56*5bc99910SRamuthevar Vadivel Murugan... 57