xref: /linux/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml (revision 70d1b1a7f8b32b78c09b30dbcfa25ba1e470568b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mixel LVDS PHY for Freescale i.MX8qm SoC
8
9maintainers:
10  - Liu Ying <victor.liu@nxp.com>
11
12description: |
13  The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
14  It converts two groups of four 7/10 bits of CMOS data into two
15  groups of four data lanes of LVDS data streams. A phase-locked
16  transmit clock is transmitted in parallel with each group of
17  data streams over a fifth LVDS link. Every cycle of the transmit
18  clock, 56/80 bits of input data are sampled and transmitted
19  through the two groups of LVDS data streams. Together with the
20  transmit clocks, the two groups of LVDS data streams form two
21  LVDS channels.
22
23  The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
24  by Control and Status Registers(CSR) module in the SoC. The CSR
25  module, as a system controller, contains the PHY's registers.
26
27properties:
28  compatible:
29    enum:
30      - fsl,imx8qm-lvds-phy
31      - mixel,28fdsoi-lvds-1250-8ch-tx-pll
32
33  "#phy-cells":
34    const: 1
35    description: |
36      Cell allows setting the LVDS channel index of the PHY.
37      Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
38
39  clocks:
40    maxItems: 1
41
42  power-domains:
43    maxItems: 1
44
45required:
46  - compatible
47  - "#phy-cells"
48  - clocks
49  - power-domains
50
51additionalProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/firmware/imx/rsrc.h>
56    phy {
57        compatible = "fsl,imx8qm-lvds-phy";
58        #phy-cells = <1>;
59        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
60        power-domains = <&pd IMX_SC_R_LVDS_0>;
61    };
62