1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A64 USB PHY 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13properties: 14 "#phy-cells": 15 const: 1 16 17 compatible: 18 oneOf: 19 - enum: 20 - allwinner,sun20i-d1-usb-phy 21 - allwinner,sun50i-a64-usb-phy 22 - items: 23 - const: allwinner,sun50i-a100-usb-phy 24 - const: allwinner,sun20i-d1-usb-phy 25 26 reg: 27 items: 28 - description: PHY Control registers 29 - description: PHY PMU0 registers 30 - description: PHY PMU1 registers 31 32 reg-names: 33 items: 34 - const: phy_ctrl 35 - const: pmu0 36 - const: pmu1 37 38 clocks: 39 items: 40 - description: USB OTG PHY bus clock 41 - description: USB Host 0 PHY bus clock 42 43 clock-names: 44 items: 45 - const: usb0_phy 46 - const: usb1_phy 47 48 resets: 49 items: 50 - description: USB OTG reset 51 - description: USB Host 1 Controller reset 52 53 reset-names: 54 items: 55 - const: usb0_reset 56 - const: usb1_reset 57 58 usb0_id_det-gpios: 59 maxItems: 1 60 description: GPIO to the USB OTG ID pin 61 62 usb0_vbus_det-gpios: 63 maxItems: 1 64 description: GPIO to the USB OTG VBUS detect pin 65 66 usb0_vbus_power-supply: 67 description: Power supply to detect the USB OTG VBUS 68 69 usb0_vbus-supply: 70 description: Regulator controlling USB OTG VBUS 71 72 usb1_vbus-supply: 73 description: Regulator controlling USB1 Host controller 74 75required: 76 - "#phy-cells" 77 - compatible 78 - clocks 79 - clock-names 80 - reg 81 - reg-names 82 - resets 83 - reset-names 84 85additionalProperties: false 86 87examples: 88 - | 89 #include <dt-bindings/gpio/gpio.h> 90 #include <dt-bindings/clock/sun50i-a64-ccu.h> 91 #include <dt-bindings/reset/sun50i-a64-ccu.h> 92 93 phy@1c19400 { 94 #phy-cells = <1>; 95 compatible = "allwinner,sun50i-a64-usb-phy"; 96 reg = <0x01c19400 0x14>, 97 <0x01c1a800 0x4>, 98 <0x01c1b800 0x4>; 99 reg-names = "phy_ctrl", 100 "pmu0", 101 "pmu1"; 102 clocks = <&ccu CLK_USB_PHY0>, 103 <&ccu CLK_USB_PHY1>; 104 clock-names = "usb0_phy", 105 "usb1_phy"; 106 resets = <&ccu RST_USB_PHY0>, 107 <&ccu RST_USB_PHY1>; 108 reset-names = "usb0_reset", 109 "usb1_reset"; 110 usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ 111 usb0_vbus_power-supply = <&usb_power_supply>; 112 usb0_vbus-supply = <®_drivevbus>; 113 usb1_vbus-supply = <®_usb1_vbus>; 114 }; 115