xref: /linux/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml (revision 7fc2cd2e4b398c57c9cf961cfea05eadbf34c05c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale(NXP) IMX8/9 DDR performance monitor
8
9maintainers:
10  - Frank Li <frank.li@nxp.com>
11
12properties:
13  compatible:
14    oneOf:
15      - enum:
16          - fsl,imx8-ddr-pmu
17          - fsl,imx8dxl-db-pmu
18          - fsl,imx8m-ddr-pmu
19          - fsl,imx8mq-ddr-pmu
20          - fsl,imx8mm-ddr-pmu
21          - fsl,imx8mn-ddr-pmu
22          - fsl,imx8mp-ddr-pmu
23          - fsl,imx93-ddr-pmu
24      - items:
25          - enum:
26              - fsl,imx8mm-ddr-pmu
27              - fsl,imx8mn-ddr-pmu
28              - fsl,imx8mq-ddr-pmu
29              - fsl,imx8mp-ddr-pmu
30          - const: fsl,imx8m-ddr-pmu
31      - items:
32          - enum:
33              - fsl,imx8dxl-ddr-pmu
34              - fsl,imx8qm-ddr-pmu
35              - fsl,imx8qxp-ddr-pmu
36          - const: fsl,imx8-ddr-pmu
37      - items:
38          - enum:
39              - fsl,imx91-ddr-pmu
40              - fsl,imx94-ddr-pmu
41              - fsl,imx95-ddr-pmu
42          - const: fsl,imx93-ddr-pmu
43
44  reg:
45    maxItems: 1
46
47  interrupts:
48    maxItems: 1
49
50  clocks:
51    maxItems: 2
52
53  clock-names:
54    items:
55      - const: ipg
56      - const: cnt
57
58required:
59  - compatible
60  - reg
61  - interrupts
62
63additionalProperties: false
64
65allOf:
66  - if:
67      properties:
68        compatible:
69          contains:
70            const: fsl,imx8dxl-db-pmu
71    then:
72      required:
73        - clocks
74        - clock-names
75    else:
76      properties:
77        clocks: false
78        clock-names: false
79
80examples:
81  - |
82    #include <dt-bindings/interrupt-controller/arm-gic.h>
83
84    ddr-pmu@5c020000 {
85        compatible = "fsl,imx8-ddr-pmu";
86        reg = <0x5c020000 0x10000>;
87        interrupt-parent = <&gic>;
88        interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
89    };
90