1*fd0ae78dSAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*fd0ae78dSAnson Huang%YAML 1.2 3*fd0ae78dSAnson Huang--- 4*fd0ae78dSAnson Huang$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml# 5*fd0ae78dSAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*fd0ae78dSAnson Huang 7*fd0ae78dSAnson Huangtitle: Freescale(NXP) IMX8 DDR performance monitor 8*fd0ae78dSAnson Huang 9*fd0ae78dSAnson Huangmaintainers: 10*fd0ae78dSAnson Huang - Frank Li <frank.li@nxp.com> 11*fd0ae78dSAnson Huang 12*fd0ae78dSAnson Huangproperties: 13*fd0ae78dSAnson Huang compatible: 14*fd0ae78dSAnson Huang enum: 15*fd0ae78dSAnson Huang - fsl,imx8-ddr-pmu 16*fd0ae78dSAnson Huang - fsl,imx8m-ddr-pmu 17*fd0ae78dSAnson Huang - fsl,imx8mp-ddr-pmu 18*fd0ae78dSAnson Huang 19*fd0ae78dSAnson Huang reg: 20*fd0ae78dSAnson Huang maxItems: 1 21*fd0ae78dSAnson Huang 22*fd0ae78dSAnson Huang interrupts: 23*fd0ae78dSAnson Huang maxItems: 1 24*fd0ae78dSAnson Huang 25*fd0ae78dSAnson Huangrequired: 26*fd0ae78dSAnson Huang - compatible 27*fd0ae78dSAnson Huang - reg 28*fd0ae78dSAnson Huang - interrupts 29*fd0ae78dSAnson Huang 30*fd0ae78dSAnson HuangadditionalProperties: false 31*fd0ae78dSAnson Huang 32*fd0ae78dSAnson Huangexamples: 33*fd0ae78dSAnson Huang - | 34*fd0ae78dSAnson Huang #include <dt-bindings/interrupt-controller/arm-gic.h> 35*fd0ae78dSAnson Huang 36*fd0ae78dSAnson Huang ddr-pmu@5c020000 { 37*fd0ae78dSAnson Huang compatible = "fsl,imx8-ddr-pmu"; 38*fd0ae78dSAnson Huang reg = <0x5c020000 0x10000>; 39*fd0ae78dSAnson Huang interrupt-parent = <&gic>; 40*fd0ae78dSAnson Huang interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 41*fd0ae78dSAnson Huang }; 42