1*2704e759SJean-Philippe Brucker# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*2704e759SJean-Philippe Brucker%YAML 1.2 3*2704e759SJean-Philippe Brucker--- 4*2704e759SJean-Philippe Brucker$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml# 5*2704e759SJean-Philippe Brucker$schema: http://devicetree.org/meta-schemas/core.yaml# 6*2704e759SJean-Philippe Brucker 7*2704e759SJean-Philippe Bruckertitle: Arm SMMUv3 Performance Monitor Counter Group 8*2704e759SJean-Philippe Brucker 9*2704e759SJean-Philippe Bruckermaintainers: 10*2704e759SJean-Philippe Brucker - Will Deacon <will@kernel.org> 11*2704e759SJean-Philippe Brucker - Robin Murphy <robin.murphy@arm.com> 12*2704e759SJean-Philippe Brucker 13*2704e759SJean-Philippe Bruckerdescription: | 14*2704e759SJean-Philippe Brucker An SMMUv3 may have several Performance Monitor Counter Group (PMCG). 15*2704e759SJean-Philippe Brucker They are standalone performance monitoring units that support both 16*2704e759SJean-Philippe Brucker architected and IMPLEMENTATION DEFINED event counters. 17*2704e759SJean-Philippe Brucker 18*2704e759SJean-Philippe Bruckerproperties: 19*2704e759SJean-Philippe Brucker $nodename: 20*2704e759SJean-Philippe Brucker pattern: "^pmu@[0-9a-f]*" 21*2704e759SJean-Philippe Brucker compatible: 22*2704e759SJean-Philippe Brucker oneOf: 23*2704e759SJean-Philippe Brucker - items: 24*2704e759SJean-Philippe Brucker - const: arm,mmu-600-pmcg 25*2704e759SJean-Philippe Brucker - const: arm,smmu-v3-pmcg 26*2704e759SJean-Philippe Brucker - const: arm,smmu-v3-pmcg 27*2704e759SJean-Philippe Brucker 28*2704e759SJean-Philippe Brucker reg: 29*2704e759SJean-Philippe Brucker items: 30*2704e759SJean-Philippe Brucker - description: Register page 0 31*2704e759SJean-Philippe Brucker - description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1 32*2704e759SJean-Philippe Brucker minItems: 1 33*2704e759SJean-Philippe Brucker 34*2704e759SJean-Philippe Brucker interrupts: 35*2704e759SJean-Philippe Brucker maxItems: 1 36*2704e759SJean-Philippe Brucker 37*2704e759SJean-Philippe Brucker msi-parent: true 38*2704e759SJean-Philippe Brucker 39*2704e759SJean-Philippe Bruckerrequired: 40*2704e759SJean-Philippe Brucker - compatible 41*2704e759SJean-Philippe Brucker - reg 42*2704e759SJean-Philippe Brucker 43*2704e759SJean-Philippe BruckeranyOf: 44*2704e759SJean-Philippe Brucker - required: 45*2704e759SJean-Philippe Brucker - interrupts 46*2704e759SJean-Philippe Brucker - required: 47*2704e759SJean-Philippe Brucker - msi-parent 48*2704e759SJean-Philippe Brucker 49*2704e759SJean-Philippe BruckeradditionalProperties: false 50*2704e759SJean-Philippe Brucker 51*2704e759SJean-Philippe Bruckerexamples: 52*2704e759SJean-Philippe Brucker - | 53*2704e759SJean-Philippe Brucker #include <dt-bindings/interrupt-controller/arm-gic.h> 54*2704e759SJean-Philippe Brucker #include <dt-bindings/interrupt-controller/irq.h> 55*2704e759SJean-Philippe Brucker 56*2704e759SJean-Philippe Brucker pmu@2b420000 { 57*2704e759SJean-Philippe Brucker compatible = "arm,smmu-v3-pmcg"; 58*2704e759SJean-Philippe Brucker reg = <0x2b420000 0x1000>, 59*2704e759SJean-Philippe Brucker <0x2b430000 0x1000>; 60*2704e759SJean-Philippe Brucker interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>; 61*2704e759SJean-Philippe Brucker msi-parent = <&its 0xff0000>; 62*2704e759SJean-Philippe Brucker }; 63*2704e759SJean-Philippe Brucker 64*2704e759SJean-Philippe Brucker pmu@2b440000 { 65*2704e759SJean-Philippe Brucker compatible = "arm,smmu-v3-pmcg"; 66*2704e759SJean-Philippe Brucker reg = <0x2b440000 0x1000>, 67*2704e759SJean-Philippe Brucker <0x2b450000 0x1000>; 68*2704e759SJean-Philippe Brucker interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>; 69*2704e759SJean-Philippe Brucker msi-parent = <&its 0xff0000>; 70*2704e759SJean-Philippe Brucker }; 71