1*7255cfb1SRobin Murphy# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*7255cfb1SRobin Murphy%YAML 1.2 3*7255cfb1SRobin Murphy--- 4*7255cfb1SRobin Murphy$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml# 5*7255cfb1SRobin Murphy$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7255cfb1SRobin Murphy 7*7255cfb1SRobin Murphytitle: Arm Coresight Performance Monitoring Unit Architecture 8*7255cfb1SRobin Murphy 9*7255cfb1SRobin Murphymaintainers: 10*7255cfb1SRobin Murphy - Robin Murphy <robin.murphy@arm.com> 11*7255cfb1SRobin Murphy 12*7255cfb1SRobin Murphyproperties: 13*7255cfb1SRobin Murphy compatible: 14*7255cfb1SRobin Murphy const: arm,coresight-pmu 15*7255cfb1SRobin Murphy 16*7255cfb1SRobin Murphy reg: 17*7255cfb1SRobin Murphy items: 18*7255cfb1SRobin Murphy - description: Register page 0 19*7255cfb1SRobin Murphy - description: Register page 1, if the PMU implements the dual-page extension 20*7255cfb1SRobin Murphy minItems: 1 21*7255cfb1SRobin Murphy 22*7255cfb1SRobin Murphy interrupts: 23*7255cfb1SRobin Murphy items: 24*7255cfb1SRobin Murphy - description: Overflow interrupt 25*7255cfb1SRobin Murphy 26*7255cfb1SRobin Murphy cpus: 27*7255cfb1SRobin Murphy description: If the PMU is associated with a particular CPU or subset of CPUs, 28*7255cfb1SRobin Murphy array of phandles to the appropriate CPU node(s) 29*7255cfb1SRobin Murphy 30*7255cfb1SRobin Murphy reg-io-width: 31*7255cfb1SRobin Murphy description: Granularity at which PMU register accesses are single-copy atomic 32*7255cfb1SRobin Murphy default: 4 33*7255cfb1SRobin Murphy enum: [4, 8] 34*7255cfb1SRobin Murphy 35*7255cfb1SRobin Murphyrequired: 36*7255cfb1SRobin Murphy - compatible 37*7255cfb1SRobin Murphy - reg 38*7255cfb1SRobin Murphy 39*7255cfb1SRobin MurphyadditionalProperties: false 40