xref: /linux/Documentation/devicetree/bindings/perf/arm,cmn.yaml (revision a1c3be890440a1769ed6f822376a3e3ab0d42994) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright 2020 Arm Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/perf/arm,cmn.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Arm CMN (Coherent Mesh Network) Performance Monitors
9
10maintainers:
11  - Robin Murphy <robin.murphy@arm.com>
12
13properties:
14  compatible:
15    const: arm,cmn-600
16
17  reg:
18    items:
19      - description: Physical address of the base (PERIPHBASE) and
20          size (up to 64MB) of the configuration address space.
21
22  interrupts:
23    minItems: 1
24    maxItems: 4
25    items:
26      - description: Overflow interrupt for DTC0
27      - description: Overflow interrupt for DTC1
28      - description: Overflow interrupt for DTC2
29      - description: Overflow interrupt for DTC3
30    description: One interrupt for each DTC domain implemented must
31      be specified, in order. DTC0 is always present.
32
33  arm,root-node:
34    $ref: /schemas/types.yaml#/definitions/uint32
35    description: Offset from PERIPHBASE of the configuration
36      discovery node (see TRM definition of ROOTNODEBASE).
37
38required:
39  - compatible
40  - reg
41  - interrupts
42  - arm,root-node
43
44additionalProperties: false
45
46examples:
47  - |
48    #include <dt-bindings/interrupt-controller/arm-gic.h>
49    #include <dt-bindings/interrupt-controller/irq.h>
50    pmu@50000000 {
51        compatible = "arm,cmn-600";
52        reg = <0x50000000 0x4000000>;
53        /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */
54        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
55        arm,root-node = <0x104000>;
56    };
57...
58