1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright 2021 Arm Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) 9 10maintainers: 11 - Suzuki K Poulose <suzuki.poulose@arm.com> 12 - Robin Murphy <robin.murphy@arm.com> 13 14description: 15 ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared 16 L3 memory system, control logic and external interfaces to form a multicore 17 cluster. The PMU enables gathering various statistics on the operation of the 18 DSU. The PMU provides independent 32-bit counters that can count any of the 19 supported events, along with a 64-bit cycle counter. The PMU is accessed via 20 CPU system registers and has no MMIO component. 21 22properties: 23 compatible: 24 const: arm,dsu-pmu 25 26 interrupts: 27 items: 28 - description: nCLUSTERPMUIRQ interrupt 29 30 cpus: 31 $ref: /schemas/types.yaml#/definitions/phandle-array 32 minItems: 1 33 maxItems: 8 34 description: List of phandles for the CPUs connected to this DSU instance. 35 36required: 37 - compatible 38 - interrupts 39 - cpus 40 41additionalProperties: false 42