xref: /linux/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml (revision 2d0b208b3b0a6a84774b860d51f2be9af8f2053f)
1*2d0b208bSRobin Murphy# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*2d0b208bSRobin Murphy# Copyright 2021 Arm Ltd.
3*2d0b208bSRobin Murphy%YAML 1.2
4*2d0b208bSRobin Murphy---
5*2d0b208bSRobin Murphy$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
6*2d0b208bSRobin Murphy$schema: http://devicetree.org/meta-schemas/core.yaml#
7*2d0b208bSRobin Murphy
8*2d0b208bSRobin Murphytitle: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
9*2d0b208bSRobin Murphy
10*2d0b208bSRobin Murphymaintainers:
11*2d0b208bSRobin Murphy  - Suzuki K Poulose <suzuki.poulose@arm.com>
12*2d0b208bSRobin Murphy  - Robin Murphy <robin.murphy@arm.com>
13*2d0b208bSRobin Murphy
14*2d0b208bSRobin Murphydescription:
15*2d0b208bSRobin Murphy  ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
16*2d0b208bSRobin Murphy  L3 memory system, control logic and external interfaces to form a multicore
17*2d0b208bSRobin Murphy  cluster. The PMU enables gathering various statistics on the operation of the
18*2d0b208bSRobin Murphy  DSU. The PMU provides independent 32-bit counters that can count any of the
19*2d0b208bSRobin Murphy  supported events, along with a 64-bit cycle counter. The PMU is accessed via
20*2d0b208bSRobin Murphy  CPU system registers and has no MMIO component.
21*2d0b208bSRobin Murphy
22*2d0b208bSRobin Murphyproperties:
23*2d0b208bSRobin Murphy  compatible:
24*2d0b208bSRobin Murphy    const: arm,dsu-pmu
25*2d0b208bSRobin Murphy
26*2d0b208bSRobin Murphy  interrupts:
27*2d0b208bSRobin Murphy    items:
28*2d0b208bSRobin Murphy      - description: nCLUSTERPMUIRQ interrupt
29*2d0b208bSRobin Murphy
30*2d0b208bSRobin Murphy  cpus:
31*2d0b208bSRobin Murphy    $ref: /schemas/types.yaml#/definitions/phandle-array
32*2d0b208bSRobin Murphy    minItems: 1
33*2d0b208bSRobin Murphy    maxItems: 8
34*2d0b208bSRobin Murphy    description: List of phandles for the CPUs connected to this DSU instance.
35*2d0b208bSRobin Murphy
36*2d0b208bSRobin Murphyrequired:
37*2d0b208bSRobin Murphy  - compatible
38*2d0b208bSRobin Murphy  - interrupts
39*2d0b208bSRobin Murphy  - cpus
40*2d0b208bSRobin Murphy
41*2d0b208bSRobin MurphyadditionalProperties: false
42