1*fd9678d3SJiucheng Xu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*fd9678d3SJiucheng Xu%YAML 1.2 3*fd9678d3SJiucheng Xu--- 4*fd9678d3SJiucheng Xu$id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml# 5*fd9678d3SJiucheng Xu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*fd9678d3SJiucheng Xu 7*fd9678d3SJiucheng Xutitle: Amlogic G12 DDR performance monitor 8*fd9678d3SJiucheng Xu 9*fd9678d3SJiucheng Xumaintainers: 10*fd9678d3SJiucheng Xu - Jiucheng Xu <jiucheng.xu@amlogic.com> 11*fd9678d3SJiucheng Xu 12*fd9678d3SJiucheng Xudescription: | 13*fd9678d3SJiucheng Xu Amlogic G12 series SoC integrate DDR bandwidth monitor. 14*fd9678d3SJiucheng Xu A timer is inside and can generate interrupt when timeout. 15*fd9678d3SJiucheng Xu The bandwidth is counted in the timer ISR. Different platform 16*fd9678d3SJiucheng Xu has different subset of event format attribute. 17*fd9678d3SJiucheng Xu 18*fd9678d3SJiucheng Xuproperties: 19*fd9678d3SJiucheng Xu compatible: 20*fd9678d3SJiucheng Xu enum: 21*fd9678d3SJiucheng Xu - amlogic,g12a-ddr-pmu 22*fd9678d3SJiucheng Xu - amlogic,g12b-ddr-pmu 23*fd9678d3SJiucheng Xu - amlogic,sm1-ddr-pmu 24*fd9678d3SJiucheng Xu 25*fd9678d3SJiucheng Xu reg: 26*fd9678d3SJiucheng Xu items: 27*fd9678d3SJiucheng Xu - description: DMC bandwidth register space. 28*fd9678d3SJiucheng Xu - description: DMC PLL register space. 29*fd9678d3SJiucheng Xu 30*fd9678d3SJiucheng Xu interrupts: 31*fd9678d3SJiucheng Xu items: 32*fd9678d3SJiucheng Xu - description: The IRQ of the inside timer timeout. 33*fd9678d3SJiucheng Xu 34*fd9678d3SJiucheng Xurequired: 35*fd9678d3SJiucheng Xu - compatible 36*fd9678d3SJiucheng Xu - reg 37*fd9678d3SJiucheng Xu - interrupts 38*fd9678d3SJiucheng Xu 39*fd9678d3SJiucheng XuadditionalProperties: false 40*fd9678d3SJiucheng Xu 41*fd9678d3SJiucheng Xuexamples: 42*fd9678d3SJiucheng Xu - | 43*fd9678d3SJiucheng Xu #include <dt-bindings/interrupt-controller/arm-gic.h> 44*fd9678d3SJiucheng Xu pmu { 45*fd9678d3SJiucheng Xu #address-cells = <2>; 46*fd9678d3SJiucheng Xu #size-cells = <2>; 47*fd9678d3SJiucheng Xu 48*fd9678d3SJiucheng Xu pmu@ff638000 { 49*fd9678d3SJiucheng Xu compatible = "amlogic,g12a-ddr-pmu"; 50*fd9678d3SJiucheng Xu reg = <0x0 0xff638000 0x0 0x100>, 51*fd9678d3SJiucheng Xu <0x0 0xff638c00 0x0 0x100>; 52*fd9678d3SJiucheng Xu interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 53*fd9678d3SJiucheng Xu }; 54*fd9678d3SJiucheng Xu }; 55