xref: /linux/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml (revision 55d0969c451159cff86949b38c39171cab962069) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx XDMA PL PCIe Root Port Bridge
8
9maintainers:
10  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-host-bridge.yaml#
14
15properties:
16  compatible:
17    enum:
18      - xlnx,xdma-host-3.00
19      - xlnx,qdma-host-3.00
20
21  reg:
22    items:
23      - description: configuration region and XDMA bridge register.
24      - description: QDMA bridge register.
25    minItems: 1
26
27  reg-names:
28    items:
29      - const: cfg
30      - const: breg
31    minItems: 1
32
33  ranges:
34    maxItems: 2
35
36  interrupts:
37    items:
38      - description: interrupt asserted when miscellaneous interrupt is received.
39      - description: msi0 interrupt asserted when an MSI is received.
40      - description: msi1 interrupt asserted when an MSI is received.
41
42  interrupt-names:
43    items:
44      - const: misc
45      - const: msi0
46      - const: msi1
47
48  interrupt-map-mask:
49    items:
50      - const: 0
51      - const: 0
52      - const: 0
53      - const: 7
54
55  interrupt-map:
56    maxItems: 4
57
58  "#interrupt-cells":
59    const: 1
60
61  interrupt-controller:
62    description: identifies the node as an interrupt controller
63    type: object
64    properties:
65      interrupt-controller: true
66
67      "#address-cells":
68        const: 0
69
70      "#interrupt-cells":
71        const: 1
72
73    required:
74      - interrupt-controller
75      - "#address-cells"
76      - "#interrupt-cells"
77
78    additionalProperties: false
79
80required:
81  - compatible
82  - reg
83  - ranges
84  - interrupts
85  - interrupt-map
86  - interrupt-map-mask
87  - "#interrupt-cells"
88  - interrupt-controller
89
90if:
91  properties:
92    compatible:
93      contains:
94        enum:
95          - xlnx,qdma-host-3.00
96then:
97  properties:
98    reg:
99      minItems: 2
100    reg-names:
101      minItems: 2
102  required:
103    - reg-names
104else:
105  properties:
106    reg:
107      maxItems: 1
108    reg-names:
109      maxItems: 1
110
111unevaluatedProperties: false
112
113examples:
114
115  - |
116    #include <dt-bindings/interrupt-controller/arm-gic.h>
117    #include <dt-bindings/interrupt-controller/irq.h>
118
119    soc {
120        #address-cells = <2>;
121        #size-cells = <2>;
122        pcie@a0000000 {
123            compatible = "xlnx,xdma-host-3.00";
124            reg = <0x0 0xa0000000 0x0 0x10000000>;
125            ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
126                     <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
127            #address-cells = <3>;
128            #size-cells = <2>;
129            #interrupt-cells = <1>;
130            device_type = "pci";
131            interrupt-parent = <&gic>;
132            interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
133                         <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
134            interrupt-names = "misc", "msi0", "msi1";
135            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
136            interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
137                            <0 0 0 2 &pcie_intc_0 1>,
138                            <0 0 0 3 &pcie_intc_0 2>,
139                            <0 0 0 4 &pcie_intc_0 3>;
140            pcie_intc_0: interrupt-controller {
141                #address-cells = <0>;
142                #interrupt-cells = <1>;
143                interrupt-controller;
144            };
145        };
146    };
147