xref: /linux/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx AXI PCIe Root Port Bridge
8
9maintainers:
10  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-host-bridge.yaml#
14
15properties:
16  compatible:
17    const: xlnx,axi-pcie-host-1.00.a
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  ranges:
26    items:
27      - description: |
28          ranges for the PCI memory regions (I/O space region is not
29          supported by hardware)
30
31  "#interrupt-cells":
32    const: 1
33
34  interrupt-controller:
35    description: identifies the node as an interrupt controller
36    type: object
37    properties:
38      interrupt-controller: true
39
40      "#address-cells":
41        const: 0
42
43      "#interrupt-cells":
44        const: 1
45
46    required:
47      - interrupt-controller
48      - "#address-cells"
49      - "#interrupt-cells"
50
51    additionalProperties: false
52
53required:
54  - compatible
55  - reg
56  - ranges
57  - interrupts
58  - interrupt-map
59  - "#interrupt-cells"
60  - interrupt-controller
61
62unevaluatedProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/interrupt-controller/arm-gic.h>
67    #include <dt-bindings/interrupt-controller/irq.h>
68
69    pcie@50000000 {
70        compatible = "xlnx,axi-pcie-host-1.00.a";
71        reg = <0x50000000 0x1000000>;
72        #address-cells = <3>;
73        #size-cells = <2>;
74        #interrupt-cells = <1>;
75        device_type = "pci";
76        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
77        interrupt-map-mask = <0 0 0 7>;
78        interrupt-map = <0 0 0 1 &pcie_intc 1>,
79                        <0 0 0 2 &pcie_intc 2>,
80                        <0 0 0 3 &pcie_intc 3>,
81                        <0 0 0 4 &pcie_intc 4>;
82        ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>;
83        pcie_intc: interrupt-controller {
84            interrupt-controller;
85            #address-cells = <0>;
86            #interrupt-cells = <1>;
87        };
88    };
89