xref: /linux/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml (revision 6e7fd890f1d6ac83805409e9c346240de2705584) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: CPM Host Controller device tree for Xilinx Versal SoCs
8
9maintainers:
10  - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-host-bridge.yaml#
14
15properties:
16  compatible:
17    enum:
18      - xlnx,versal-cpm-host-1.00
19      - xlnx,versal-cpm5-host
20
21  reg:
22    items:
23      - description: CPM system level control and status registers.
24      - description: Configuration space region and bridge registers.
25      - description: CPM5 control and status registers.
26    minItems: 2
27
28  reg-names:
29    items:
30      - const: cpm_slcr
31      - const: cfg
32      - const: cpm_csr
33    minItems: 2
34
35  interrupts:
36    maxItems: 1
37
38  msi-map:
39    description:
40      Maps a Requester ID to an MSI controller and associated MSI sideband data.
41
42  ranges:
43    maxItems: 2
44
45  "#interrupt-cells":
46    const: 1
47
48  interrupt-controller:
49    description: Interrupt controller node for handling legacy PCI interrupts.
50    type: object
51    additionalProperties: false
52
53    properties:
54      "#address-cells":
55        const: 0
56
57      "#interrupt-cells":
58        const: 1
59
60      interrupt-controller: true
61
62required:
63  - reg
64  - reg-names
65  - "#interrupt-cells"
66  - interrupts
67  - interrupt-map
68  - interrupt-map-mask
69  - bus-range
70  - msi-map
71  - interrupt-controller
72
73unevaluatedProperties: false
74
75examples:
76  - |
77
78    versal {
79               #address-cells = <2>;
80               #size-cells = <2>;
81               cpm_pcie: pcie@fca10000 {
82                       compatible = "xlnx,versal-cpm-host-1.00";
83                       device_type = "pci";
84                       #address-cells = <3>;
85                       #interrupt-cells = <1>;
86                       #size-cells = <2>;
87                       interrupts = <0 72 4>;
88                       interrupt-parent = <&gic>;
89                       interrupt-map-mask = <0 0 0 7>;
90                       interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
91                                       <0 0 0 2 &pcie_intc_0 1>,
92                                       <0 0 0 3 &pcie_intc_0 2>,
93                                       <0 0 0 4 &pcie_intc_0 3>;
94                       bus-range = <0x00 0xff>;
95                       ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
96                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
97                       msi-map = <0x0 &its_gic 0x0 0x10000>;
98                       reg = <0x0 0xfca10000 0x0 0x1000>,
99                             <0x6 0x00000000 0x0 0x10000000>;
100                       reg-names = "cpm_slcr", "cfg";
101                       pcie_intc_0: interrupt-controller {
102                               #address-cells = <0>;
103                               #interrupt-cells = <1>;
104                               interrupt-controller;
105                       };
106               };
107
108               cpm5_pcie: pcie@fcdd0000 {
109                       compatible = "xlnx,versal-cpm5-host";
110                       device_type = "pci";
111                       #address-cells = <3>;
112                       #interrupt-cells = <1>;
113                       #size-cells = <2>;
114                       interrupts = <0 72 4>;
115                       interrupt-parent = <&gic>;
116                       interrupt-map-mask = <0 0 0 7>;
117                       interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
118                                       <0 0 0 2 &pcie_intc_1 1>,
119                                       <0 0 0 3 &pcie_intc_1 2>,
120                                       <0 0 0 4 &pcie_intc_1 3>;
121                       bus-range = <0x00 0xff>;
122                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
123                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
124                       msi-map = <0x0 &its_gic 0x0 0x10000>;
125                       reg = <0x00 0xfcdd0000 0x00 0x1000>,
126                             <0x06 0x00000000 0x00 0x1000000>,
127                             <0x00 0xfce20000 0x00 0x1000000>;
128                       reg-names = "cpm_slcr", "cfg", "cpm_csr";
129
130                       pcie_intc_1: interrupt-controller {
131                               #address-cells = <0>;
132                               #interrupt-cells = <1>;
133                               interrupt-controller;
134                       };
135               };
136
137    };
138