xref: /linux/Documentation/devicetree/bindings/pci/v3,v360epc-pci.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/v3,v360epc-pci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: V3 Semiconductor V360 EPC PCI bridge
8
9maintainers:
10  - Linus Walleij <linus.walleij@linaro.org>
11
12description:
13  This bridge is found in the ARM Integrator/AP (Application Platform)
14
15allOf:
16  - $ref: /schemas/pci/pci-host-bridge.yaml#
17
18properties:
19  compatible:
20    items:
21      - const: arm,integrator-ap-pci
22      - const: v3,v360epc-pci
23
24  reg:
25    items:
26      - description: V3 host bridge controller
27      - description: Configuration space
28
29  clocks:
30    maxItems: 1
31
32  dma-ranges:
33    maxItems: 2
34    description:
35      The inbound ranges must be aligned to a 1MB boundary, and may be 1MB, 2MB,
36      4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The
37      memory should be marked as pre-fetchable.
38
39  interrupts:
40    description: Bus Error IRQ
41    maxItems: 1
42
43  ranges:
44    description:
45      The non-prefetchable and prefetchable memory windows must each be exactly
46      256MB (0x10000000) in size. The prefetchable memory window must be
47      immediately adjacent to the non-prefetchable memory window.
48
49required:
50  - compatible
51  - reg
52  - clocks
53  - dma-ranges
54  - "#interrupt-cells"
55  - interrupt-map
56  - interrupt-map-mask
57
58unevaluatedProperties: false
59
60examples:
61  - |
62    pci@62000000 {
63        compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
64        #interrupt-cells = <1>;
65        #size-cells = <2>;
66        #address-cells = <3>;
67        reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
68        device_type = "pci";
69        interrupt-parent = <&pic>;
70        interrupts = <17>; /* Bus error IRQ */
71        clocks = <&pciclk>;
72        ranges = <0x01000000 0 0x00000000 0x60000000 0 0x01000000>,     /* 16 MiB @ LB 60000000 */
73                 <0x02000000 0 0x40000000 0x40000000 0 0x10000000>,     /* 256 MiB @ LB 40000000 1:1 */
74                 <0x42000000 0 0x50000000 0x50000000 0 0x10000000>;     /* 256 MiB @ LB 50000000 1:1 */
75        dma-ranges = <0x02000000 0 0x20000000 0x20000000 0 0x20000000>, /* EBI: 512 MB @ LB 20000000 1:1 */
76                     <0x02000000 0 0x80000000 0x80000000 0 0x40000000>; /* CM alias: 1GB @ LB 80000000 */
77        interrupt-map-mask = <0xf800 0 0 0x7>;
78        interrupt-map =
79            /* IDSEL 9 */
80            <0x4800 0 0 1 &pic 13>, /* INT A on slot 9 is irq 13 */
81            <0x4800 0 0 2 &pic 14>, /* INT B on slot 9 is irq 14 */
82            <0x4800 0 0 3 &pic 15>, /* INT C on slot 9 is irq 15 */
83            <0x4800 0 0 4 &pic 16>, /* INT D on slot 9 is irq 16 */
84            /* IDSEL 10 */
85            <0x5000 0 0 1 &pic 14>, /* INT A on slot 10 is irq 14 */
86            <0x5000 0 0 2 &pic 15>, /* INT B on slot 10 is irq 15 */
87            <0x5000 0 0 3 &pic 16>, /* INT C on slot 10 is irq 16 */
88            <0x5000 0 0 4 &pic 13>, /* INT D on slot 10 is irq 13 */
89            /* IDSEL 11 */
90            <0x5800 0 0 1 &pic 15>, /* INT A on slot 11 is irq 15 */
91            <0x5800 0 0 2 &pic 16>, /* INT B on slot 11 is irq 16 */
92            <0x5800 0 0 3 &pic 13>, /* INT C on slot 11 is irq 13 */
93            <0x5800 0 0 4 &pic 14>, /* INT D on slot 11 is irq 14 */
94            /* IDSEL 12 */
95            <0x6000 0 0 1 &pic 16>, /* INT A on slot 12 is irq 16 */
96            <0x6000 0 0 2 &pic 13>, /* INT B on slot 12 is irq 13 */
97            <0x6000 0 0 3 &pic 14>, /* INT C on slot 12 is irq 14 */
98            <0x6000 0 0 4 &pic 15>; /* INT D on slot 12 is irq 15 */
99    };
100...
101