xref: /linux/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml (revision a0efa2f362a69e47b9d8b48f770ef3a0249a7911) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI J721E PCI Host (PCIe Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13properties:
14  compatible:
15    oneOf:
16      - const: ti,j721e-pcie-host
17      - const: ti,j784s4-pcie-host
18      - description: PCIe controller in AM64
19        items:
20          - const: ti,am64-pcie-host
21          - const: ti,j721e-pcie-host
22      - description: PCIe controller in J7200
23        items:
24          - const: ti,j7200-pcie-host
25          - const: ti,j721e-pcie-host
26      - description: PCIe controller in J722S
27        items:
28          - const: ti,j722s-pcie-host
29          - const: ti,j721e-pcie-host
30
31  reg:
32    maxItems: 4
33
34  reg-names:
35    items:
36      - const: intd_cfg
37      - const: user_cfg
38      - const: reg
39      - const: cfg
40
41  ti,syscon-acspcie-proxy-ctrl:
42    $ref: /schemas/types.yaml#/definitions/phandle-array
43    items:
44      - items:
45          - description: Phandle to the ACSPCIE Proxy Control Register
46          - description: Bitmask corresponding to the PAD IO Buffer
47                         output enable fields (Active Low).
48    description: Specifier for enabling the ACSPCIE PAD outputs to drive
49                 the reference clock to the Endpoint device.
50
51  ti,syscon-pcie-ctrl:
52    $ref: /schemas/types.yaml#/definitions/phandle-array
53    items:
54      - items:
55          - description: Phandle to the SYSCON entry
56          - description: pcie_ctrl register offset within SYSCON
57    description: Specifier for configuring PCIe mode and link speed.
58
59  power-domains:
60    maxItems: 1
61
62  clocks:
63    minItems: 1
64    maxItems: 2
65    description: |+
66      clock-specifier to represent input to the PCIe for 1 item.
67      2nd item if present represents reference clock to the connector.
68
69  clock-names:
70    minItems: 1
71    items:
72      - const: fck
73      - const: pcie_refclk
74
75  dma-coherent: true
76
77  vendor-id:
78    const: 0x104c
79
80  device-id:
81    enum:
82      - 0xb00d
83      - 0xb00f
84      - 0xb010
85      - 0xb012
86      - 0xb013
87
88  msi-map: true
89
90  interrupts:
91    maxItems: 1
92
93  interrupt-names:
94    items:
95      - const: link_state
96
97  interrupt-controller:
98    type: object
99    additionalProperties: false
100
101    properties:
102      interrupt-controller: true
103
104      '#interrupt-cells':
105        const: 1
106
107      interrupts:
108        maxItems: 1
109
110allOf:
111  - $ref: cdns-pcie-host.yaml#
112  - if:
113      properties:
114        compatible:
115          enum:
116            - ti,am64-pcie-host
117    then:
118      properties:
119        num-lanes:
120          const: 1
121
122  - if:
123      properties:
124        compatible:
125          enum:
126            - ti,j7200-pcie-host
127            - ti,j721e-pcie-host
128    then:
129      properties:
130        num-lanes:
131          minimum: 1
132          maximum: 2
133
134  - if:
135      properties:
136        compatible:
137          enum:
138            - ti,j784s4-pcie-host
139    then:
140      properties:
141        num-lanes:
142          minimum: 1
143          maximum: 4
144
145required:
146  - compatible
147  - reg
148  - reg-names
149  - ti,syscon-pcie-ctrl
150  - max-link-speed
151  - num-lanes
152  - power-domains
153  - clocks
154  - clock-names
155  - vendor-id
156  - device-id
157  - msi-map
158  - dma-ranges
159  - ranges
160  - reset-gpios
161  - phys
162  - phy-names
163
164unevaluatedProperties: false
165
166examples:
167  - |
168    #include <dt-bindings/soc/ti,sci_pm_domain.h>
169    #include <dt-bindings/gpio/gpio.h>
170
171    bus {
172        #address-cells = <2>;
173        #size-cells = <2>;
174
175        pcie0_rc: pcie@2900000 {
176            compatible = "ti,j721e-pcie-host";
177            reg = <0x00 0x02900000 0x00 0x1000>,
178                  <0x00 0x02907000 0x00 0x400>,
179                  <0x00 0x0d000000 0x00 0x00800000>,
180                  <0x00 0x10000000 0x00 0x00001000>;
181            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
182            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
183            max-link-speed = <3>;
184            num-lanes = <2>;
185            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
186            clocks = <&k3_clks 239 1>;
187            clock-names = "fck";
188            device_type = "pci";
189            #address-cells = <3>;
190            #size-cells = <2>;
191            bus-range = <0x0 0xf>;
192            vendor-id = <0x104c>;
193            device-id = <0xb00d>;
194            msi-map = <0x0 &gic_its 0x0 0x10000>;
195            dma-coherent;
196            reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
197            phys = <&serdes0_pcie_link>;
198            phy-names = "pcie-phy";
199            ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
200                     <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
201            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
202        };
203    };
204