xref: /linux/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml (revision 4fd18fc38757217c746aa063ba9e4729814dc737) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI J721E PCI Host (PCIe Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13allOf:
14  - $ref: "cdns-pcie-host.yaml#"
15
16properties:
17  compatible:
18    oneOf:
19      - description: PCIe controller in J7200
20        items:
21          - const: ti,j7200-pcie-host
22          - const: ti,j721e-pcie-host
23      - description: PCIe controller in J721E
24        items:
25          - const: ti,j721e-pcie-host
26
27  reg:
28    maxItems: 4
29
30  reg-names:
31    items:
32      - const: intd_cfg
33      - const: user_cfg
34      - const: reg
35      - const: cfg
36
37  ti,syscon-pcie-ctrl:
38    $ref: /schemas/types.yaml#/definitions/phandle-array
39    items:
40      - items:
41          - description: Phandle to the SYSCON entry
42          - description: pcie_ctrl register offset within SYSCON
43    description: Specifier for configuring PCIe mode and link speed.
44
45  power-domains:
46    maxItems: 1
47
48  clocks:
49    maxItems: 1
50    description: clock-specifier to represent input to the PCIe
51
52  clock-names:
53    items:
54      - const: fck
55
56  vendor-id:
57    const: 0x104c
58
59  device-id:
60    oneOf:
61      - items:
62          - const: 0xb00d
63      - items:
64          - const: 0xb00f
65
66  msi-map: true
67
68required:
69  - compatible
70  - reg
71  - reg-names
72  - ti,syscon-pcie-ctrl
73  - max-link-speed
74  - num-lanes
75  - power-domains
76  - clocks
77  - clock-names
78  - vendor-id
79  - device-id
80  - msi-map
81  - dma-coherent
82  - dma-ranges
83  - ranges
84  - reset-gpios
85  - phys
86  - phy-names
87
88unevaluatedProperties: false
89
90examples:
91  - |
92    #include <dt-bindings/soc/ti,sci_pm_domain.h>
93    #include <dt-bindings/gpio/gpio.h>
94
95    bus {
96        #address-cells = <2>;
97        #size-cells = <2>;
98
99        pcie0_rc: pcie@2900000 {
100            compatible = "ti,j721e-pcie-host";
101            reg = <0x00 0x02900000 0x00 0x1000>,
102                  <0x00 0x02907000 0x00 0x400>,
103                  <0x00 0x0d000000 0x00 0x00800000>,
104                  <0x00 0x10000000 0x00 0x00001000>;
105            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
106            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
107            max-link-speed = <3>;
108            num-lanes = <2>;
109            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
110            clocks = <&k3_clks 239 1>;
111            clock-names = "fck";
112            device_type = "pci";
113            #address-cells = <3>;
114            #size-cells = <2>;
115            bus-range = <0x0 0xf>;
116            vendor-id = <0x104c>;
117            device-id = <0xb00d>;
118            msi-map = <0x0 &gic_its 0x0 0x10000>;
119            dma-coherent;
120            reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
121            phys = <&serdes0_pcie_link>;
122            phy-names = "pcie-phy";
123            ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
124                     <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
125            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
126        };
127    };
128