xref: /linux/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml (revision 266aa3b4812e97942a8ce5c7aafa7da059f7b5b8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI J721E PCI Host (PCIe Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13properties:
14  compatible:
15    oneOf:
16      - const: ti,j721e-pcie-host
17      - const: ti,j784s4-pcie-host
18      - description: PCIe controller in AM64
19        items:
20          - const: ti,am64-pcie-host
21          - const: ti,j721e-pcie-host
22      - description: PCIe controller in J7200
23        items:
24          - const: ti,j7200-pcie-host
25          - const: ti,j721e-pcie-host
26      - description: PCIe controller in J722S
27        items:
28          - const: ti,j722s-pcie-host
29          - const: ti,j721e-pcie-host
30
31  reg:
32    maxItems: 4
33
34  reg-names:
35    items:
36      - const: intd_cfg
37      - const: user_cfg
38      - const: reg
39      - const: cfg
40
41  ti,syscon-pcie-ctrl:
42    $ref: /schemas/types.yaml#/definitions/phandle-array
43    items:
44      - items:
45          - description: Phandle to the SYSCON entry
46          - description: pcie_ctrl register offset within SYSCON
47    description: Specifier for configuring PCIe mode and link speed.
48
49  power-domains:
50    maxItems: 1
51
52  clocks:
53    minItems: 1
54    maxItems: 2
55    description: |+
56      clock-specifier to represent input to the PCIe for 1 item.
57      2nd item if present represents reference clock to the connector.
58
59  clock-names:
60    minItems: 1
61    items:
62      - const: fck
63      - const: pcie_refclk
64
65  dma-coherent: true
66
67  vendor-id:
68    const: 0x104c
69
70  device-id:
71    enum:
72      - 0xb00d
73      - 0xb00f
74      - 0xb010
75      - 0xb012
76      - 0xb013
77
78  msi-map: true
79
80  interrupts:
81    maxItems: 1
82
83  interrupt-names:
84    items:
85      - const: link_state
86
87  interrupt-controller:
88    type: object
89    additionalProperties: false
90
91    properties:
92      interrupt-controller: true
93
94      '#interrupt-cells':
95        const: 1
96
97      interrupts:
98        maxItems: 1
99
100allOf:
101  - $ref: cdns-pcie-host.yaml#
102  - if:
103      properties:
104        compatible:
105          enum:
106            - ti,am64-pcie-host
107    then:
108      properties:
109        num-lanes:
110          const: 1
111
112  - if:
113      properties:
114        compatible:
115          enum:
116            - ti,j7200-pcie-host
117            - ti,j721e-pcie-host
118    then:
119      properties:
120        num-lanes:
121          minimum: 1
122          maximum: 2
123
124  - if:
125      properties:
126        compatible:
127          enum:
128            - ti,j784s4-pcie-host
129    then:
130      properties:
131        num-lanes:
132          minimum: 1
133          maximum: 4
134
135required:
136  - compatible
137  - reg
138  - reg-names
139  - ti,syscon-pcie-ctrl
140  - max-link-speed
141  - num-lanes
142  - power-domains
143  - clocks
144  - clock-names
145  - vendor-id
146  - device-id
147  - msi-map
148  - dma-ranges
149  - ranges
150  - reset-gpios
151  - phys
152  - phy-names
153
154unevaluatedProperties: false
155
156examples:
157  - |
158    #include <dt-bindings/soc/ti,sci_pm_domain.h>
159    #include <dt-bindings/gpio/gpio.h>
160
161    bus {
162        #address-cells = <2>;
163        #size-cells = <2>;
164
165        pcie0_rc: pcie@2900000 {
166            compatible = "ti,j721e-pcie-host";
167            reg = <0x00 0x02900000 0x00 0x1000>,
168                  <0x00 0x02907000 0x00 0x400>,
169                  <0x00 0x0d000000 0x00 0x00800000>,
170                  <0x00 0x10000000 0x00 0x00001000>;
171            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
172            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
173            max-link-speed = <3>;
174            num-lanes = <2>;
175            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
176            clocks = <&k3_clks 239 1>;
177            clock-names = "fck";
178            device_type = "pci";
179            #address-cells = <3>;
180            #size-cells = <2>;
181            bus-range = <0x0 0xf>;
182            vendor-id = <0x104c>;
183            device-id = <0xb00d>;
184            msi-map = <0x0 &gic_its 0x0 0x10000>;
185            dma-coherent;
186            reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
187            phys = <&serdes0_pcie_link>;
188            phy-names = "pcie-phy";
189            ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
190                     <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
191            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
192        };
193    };
194