xref: /linux/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml (revision f3956ebb3bf06ab2266ad5ee2214aed46405810c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI AM65 PCI Endpoint
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13allOf:
14  - $ref: pci-ep.yaml#
15
16properties:
17  compatible:
18    enum:
19      - ti,am654-pcie-ep
20
21  reg:
22    maxItems: 4
23
24  reg-names:
25    items:
26      - const: app
27      - const: dbics
28      - const: addr_space
29      - const: atu
30
31  power-domains:
32    maxItems: 1
33
34  ti,syscon-pcie-mode:
35    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
36    $ref: /schemas/types.yaml#/definitions/phandle
37
38  interrupts:
39    minItems: 1
40
41  dma-coherent: true
42
43required:
44  - compatible
45  - reg
46  - reg-names
47  - max-link-speed
48  - power-domains
49  - ti,syscon-pcie-mode
50  - dma-coherent
51
52unevaluatedProperties: false
53
54examples:
55  - |
56    #include <dt-bindings/interrupt-controller/arm-gic.h>
57    #include <dt-bindings/interrupt-controller/irq.h>
58    #include <dt-bindings/soc/ti,sci_pm_domain.h>
59
60    pcie0_ep: pcie-ep@5500000 {
61        compatible = "ti,am654-pcie-ep";
62        reg =  <0x5500000 0x1000>,
63               <0x5501000 0x1000>,
64               <0x10000000 0x8000000>,
65               <0x5506000 0x1000>;
66        reg-names = "app", "dbics", "addr_space", "atu";
67        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
68        ti,syscon-pcie-mode = <&pcie0_mode>;
69        num-ib-windows = <16>;
70        num-ob-windows = <16>;
71        max-link-speed = <2>;
72        dma-coherent;
73        interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
74    };
75