xref: /linux/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml (revision 2f2c7254931f41b5736e3ba12aaa9ac1bbeeeb92)
1*b8ef623fSChristian Bruel# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*b8ef623fSChristian Bruel%YAML 1.2
3*b8ef623fSChristian Bruel---
4*b8ef623fSChristian Bruel$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#
5*b8ef623fSChristian Bruel$schema: http://devicetree.org/meta-schemas/core.yaml#
6*b8ef623fSChristian Bruel
7*b8ef623fSChristian Brueltitle: STMicroelectronics STM32MP25 PCIe Endpoint
8*b8ef623fSChristian Bruel
9*b8ef623fSChristian Bruelmaintainers:
10*b8ef623fSChristian Bruel  - Christian Bruel <christian.bruel@foss.st.com>
11*b8ef623fSChristian Bruel
12*b8ef623fSChristian Brueldescription:
13*b8ef623fSChristian Bruel  PCIe endpoint controller based on the Synopsys DesignWare PCIe core.
14*b8ef623fSChristian Bruel
15*b8ef623fSChristian BruelallOf:
16*b8ef623fSChristian Bruel  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
17*b8ef623fSChristian Bruel  - $ref: /schemas/pci/st,stm32-pcie-common.yaml#
18*b8ef623fSChristian Bruel
19*b8ef623fSChristian Bruelproperties:
20*b8ef623fSChristian Bruel  compatible:
21*b8ef623fSChristian Bruel    const: st,stm32mp25-pcie-ep
22*b8ef623fSChristian Bruel
23*b8ef623fSChristian Bruel  reg:
24*b8ef623fSChristian Bruel    items:
25*b8ef623fSChristian Bruel      - description: Data Bus Interface (DBI) registers.
26*b8ef623fSChristian Bruel      - description: Data Bus Interface (DBI) shadow registers.
27*b8ef623fSChristian Bruel      - description: Internal Address Translation Unit (iATU) registers.
28*b8ef623fSChristian Bruel      - description: PCIe configuration registers.
29*b8ef623fSChristian Bruel
30*b8ef623fSChristian Bruel  reg-names:
31*b8ef623fSChristian Bruel    items:
32*b8ef623fSChristian Bruel      - const: dbi
33*b8ef623fSChristian Bruel      - const: dbi2
34*b8ef623fSChristian Bruel      - const: atu
35*b8ef623fSChristian Bruel      - const: addr_space
36*b8ef623fSChristian Bruel
37*b8ef623fSChristian Bruel  reset-gpios:
38*b8ef623fSChristian Bruel    description: GPIO controlled connection to PERST# signal
39*b8ef623fSChristian Bruel    maxItems: 1
40*b8ef623fSChristian Bruel
41*b8ef623fSChristian Bruel  phys:
42*b8ef623fSChristian Bruel    maxItems: 1
43*b8ef623fSChristian Bruel
44*b8ef623fSChristian Bruelrequired:
45*b8ef623fSChristian Bruel  - phys
46*b8ef623fSChristian Bruel  - reset-gpios
47*b8ef623fSChristian Bruel
48*b8ef623fSChristian BruelunevaluatedProperties: false
49*b8ef623fSChristian Bruel
50*b8ef623fSChristian Bruelexamples:
51*b8ef623fSChristian Bruel  - |
52*b8ef623fSChristian Bruel    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
53*b8ef623fSChristian Bruel    #include <dt-bindings/gpio/gpio.h>
54*b8ef623fSChristian Bruel    #include <dt-bindings/phy/phy.h>
55*b8ef623fSChristian Bruel    #include <dt-bindings/reset/st,stm32mp25-rcc.h>
56*b8ef623fSChristian Bruel
57*b8ef623fSChristian Bruel    pcie-ep@48400000 {
58*b8ef623fSChristian Bruel        compatible = "st,stm32mp25-pcie-ep";
59*b8ef623fSChristian Bruel        reg = <0x48400000 0x400000>,
60*b8ef623fSChristian Bruel              <0x48500000 0x100000>,
61*b8ef623fSChristian Bruel              <0x48700000 0x80000>,
62*b8ef623fSChristian Bruel              <0x10000000 0x10000000>;
63*b8ef623fSChristian Bruel        reg-names = "dbi", "dbi2", "atu", "addr_space";
64*b8ef623fSChristian Bruel        clocks = <&rcc CK_BUS_PCIE>;
65*b8ef623fSChristian Bruel        phys = <&combophy PHY_TYPE_PCIE>;
66*b8ef623fSChristian Bruel        resets = <&rcc PCIE_R>;
67*b8ef623fSChristian Bruel        pinctrl-names = "default", "init";
68*b8ef623fSChristian Bruel        pinctrl-0 = <&pcie_pins_a>;
69*b8ef623fSChristian Bruel        pinctrl-1 = <&pcie_init_pins_a>;
70*b8ef623fSChristian Bruel        reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
71*b8ef623fSChristian Bruel        access-controllers = <&rifsc 68>;
72*b8ef623fSChristian Bruel        power-domains = <&CLUSTER_PD>;
73*b8ef623fSChristian Bruel    };
74