1*0f8b97d8SMauro Carvalho Chehab# SPDX-License-Identifier: GPL-2.0 2*0f8b97d8SMauro Carvalho Chehab%YAML 1.2 3*0f8b97d8SMauro Carvalho Chehab--- 4*0f8b97d8SMauro Carvalho Chehab$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml# 5*0f8b97d8SMauro Carvalho Chehab$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0f8b97d8SMauro Carvalho Chehab 7*0f8b97d8SMauro Carvalho Chehabtitle: Synopsys DesignWare PCIe endpoint interface 8*0f8b97d8SMauro Carvalho Chehab 9*0f8b97d8SMauro Carvalho Chehabmaintainers: 10*0f8b97d8SMauro Carvalho Chehab - Jingoo Han <jingoohan1@gmail.com> 11*0f8b97d8SMauro Carvalho Chehab - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 12*0f8b97d8SMauro Carvalho Chehab 13*0f8b97d8SMauro Carvalho Chehabdescription: | 14*0f8b97d8SMauro Carvalho Chehab Synopsys DesignWare PCIe host controller endpoint 15*0f8b97d8SMauro Carvalho Chehab 16*0f8b97d8SMauro Carvalho ChehaballOf: 17*0f8b97d8SMauro Carvalho Chehab - $ref: /schemas/pci/pci-ep.yaml# 18*0f8b97d8SMauro Carvalho Chehab 19*0f8b97d8SMauro Carvalho Chehabproperties: 20*0f8b97d8SMauro Carvalho Chehab compatible: 21*0f8b97d8SMauro Carvalho Chehab anyOf: 22*0f8b97d8SMauro Carvalho Chehab - {} 23*0f8b97d8SMauro Carvalho Chehab - const: snps,dw-pcie-ep 24*0f8b97d8SMauro Carvalho Chehab 25*0f8b97d8SMauro Carvalho Chehab reg: 26*0f8b97d8SMauro Carvalho Chehab description: | 27*0f8b97d8SMauro Carvalho Chehab It should contain Data Bus Interface (dbi) and config registers for all 28*0f8b97d8SMauro Carvalho Chehab versions. 29*0f8b97d8SMauro Carvalho Chehab For designware core version >= 4.80, it may contain ATU address space. 30*0f8b97d8SMauro Carvalho Chehab minItems: 2 31*0f8b97d8SMauro Carvalho Chehab maxItems: 4 32*0f8b97d8SMauro Carvalho Chehab 33*0f8b97d8SMauro Carvalho Chehab reg-names: 34*0f8b97d8SMauro Carvalho Chehab minItems: 2 35*0f8b97d8SMauro Carvalho Chehab maxItems: 4 36*0f8b97d8SMauro Carvalho Chehab items: 37*0f8b97d8SMauro Carvalho Chehab enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl] 38*0f8b97d8SMauro Carvalho Chehab 39*0f8b97d8SMauro Carvalho Chehab reset-gpio: 40*0f8b97d8SMauro Carvalho Chehab description: GPIO pin number of PERST# signal 41*0f8b97d8SMauro Carvalho Chehab maxItems: 1 42*0f8b97d8SMauro Carvalho Chehab deprecated: true 43*0f8b97d8SMauro Carvalho Chehab 44*0f8b97d8SMauro Carvalho Chehab reset-gpios: 45*0f8b97d8SMauro Carvalho Chehab description: GPIO controlled connection to PERST# signal 46*0f8b97d8SMauro Carvalho Chehab maxItems: 1 47*0f8b97d8SMauro Carvalho Chehab 48*0f8b97d8SMauro Carvalho Chehab snps,enable-cdm-check: 49*0f8b97d8SMauro Carvalho Chehab type: boolean 50*0f8b97d8SMauro Carvalho Chehab description: | 51*0f8b97d8SMauro Carvalho Chehab This is a boolean property and if present enables 52*0f8b97d8SMauro Carvalho Chehab automatic checking of CDM (Configuration Dependent Module) registers 53*0f8b97d8SMauro Carvalho Chehab for data corruption. CDM registers include standard PCIe configuration 54*0f8b97d8SMauro Carvalho Chehab space registers, Port Logic registers, DMA and iATU (internal Address 55*0f8b97d8SMauro Carvalho Chehab Translation Unit) registers. 56*0f8b97d8SMauro Carvalho Chehab 57*0f8b97d8SMauro Carvalho Chehab num-ib-windows: 58*0f8b97d8SMauro Carvalho Chehab description: number of inbound address translation windows 59*0f8b97d8SMauro Carvalho Chehab maxItems: 1 60*0f8b97d8SMauro Carvalho Chehab deprecated: true 61*0f8b97d8SMauro Carvalho Chehab 62*0f8b97d8SMauro Carvalho Chehab num-ob-windows: 63*0f8b97d8SMauro Carvalho Chehab description: number of outbound address translation windows 64*0f8b97d8SMauro Carvalho Chehab maxItems: 1 65*0f8b97d8SMauro Carvalho Chehab deprecated: true 66*0f8b97d8SMauro Carvalho Chehab 67*0f8b97d8SMauro Carvalho Chehab max-functions: 68*0f8b97d8SMauro Carvalho Chehab $ref: /schemas/types.yaml#/definitions/uint32 69*0f8b97d8SMauro Carvalho Chehab description: maximum number of functions that can be configured 70*0f8b97d8SMauro Carvalho Chehab 71*0f8b97d8SMauro Carvalho Chehabrequired: 72*0f8b97d8SMauro Carvalho Chehab - reg 73*0f8b97d8SMauro Carvalho Chehab - reg-names 74*0f8b97d8SMauro Carvalho Chehab - compatible 75*0f8b97d8SMauro Carvalho Chehab 76*0f8b97d8SMauro Carvalho ChehabunevaluatedProperties: false 77*0f8b97d8SMauro Carvalho Chehab 78*0f8b97d8SMauro Carvalho Chehabexamples: 79*0f8b97d8SMauro Carvalho Chehab - | 80*0f8b97d8SMauro Carvalho Chehab bus { 81*0f8b97d8SMauro Carvalho Chehab #address-cells = <1>; 82*0f8b97d8SMauro Carvalho Chehab #size-cells = <1>; 83*0f8b97d8SMauro Carvalho Chehab pcie-ep@dfd00000 { 84*0f8b97d8SMauro Carvalho Chehab compatible = "snps,dw-pcie-ep"; 85*0f8b97d8SMauro Carvalho Chehab reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ 86*0f8b97d8SMauro Carvalho Chehab <0xdfc01000 0x0001000>, /* IP registers 2 */ 87*0f8b97d8SMauro Carvalho Chehab <0xd0000000 0x2000000>; /* Configuration space */ 88*0f8b97d8SMauro Carvalho Chehab reg-names = "dbi", "dbi2", "addr_space"; 89*0f8b97d8SMauro Carvalho Chehab }; 90*0f8b97d8SMauro Carvalho Chehab }; 91