xref: /linux/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml (revision 29583dfcd2dd72c766422bd05c16f06c6b1fb356) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung SoC series PCIe Host Controller
8
9maintainers:
10  - Marek Szyprowski <m.szyprowski@samsung.com>
11  - Jaehoon Chung <jh80.chung@samsung.com>
12
13description: |+
14  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
15  PCIe IP and thus inherits all the common properties defined in
16  snps,dw-pcie.yaml.
17
18allOf:
19  - $ref: /schemas/pci/snps,dw-pcie.yaml#
20
21properties:
22  compatible:
23    const: samsung,exynos5433-pcie
24
25  reg:
26    items:
27      - description: Data Bus Interface (DBI) registers.
28      - description: External Local Bus interface (ELBI) registers.
29      - description: PCIe configuration space region.
30
31  reg-names:
32    items:
33      - const: dbi
34      - const: elbi
35      - const: config
36
37  interrupts:
38    maxItems: 1
39
40  clocks:
41    items:
42      - description: PCIe bridge clock
43      - description: PCIe bus clock
44
45  clock-names:
46    items:
47      - const: pcie
48      - const: pcie_bus
49
50  phys:
51    maxItems: 1
52
53  vdd10-supply:
54    description:
55      Phandle to a regulator that provides 1.0V power to the PCIe block.
56
57  vdd18-supply:
58    description:
59      Phandle to a regulator that provides 1.8V power to the PCIe block.
60
61  num-lanes:
62    const: 1
63
64  num-viewport:
65    const: 3
66
67required:
68  - reg
69  - reg-names
70  - interrupts
71  - "#address-cells"
72  - "#size-cells"
73  - "#interrupt-cells"
74  - interrupt-map
75  - interrupt-map-mask
76  - ranges
77  - bus-range
78  - device_type
79  - num-lanes
80  - num-viewport
81  - clocks
82  - clock-names
83  - phys
84  - vdd10-supply
85  - vdd18-supply
86
87unevaluatedProperties: false
88
89examples:
90  - |
91    #include <dt-bindings/interrupt-controller/irq.h>
92    #include <dt-bindings/interrupt-controller/arm-gic.h>
93    #include <dt-bindings/clock/exynos5433.h>
94
95    pcie: pcie@15700000 {
96        compatible = "samsung,exynos5433-pcie";
97        reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
98        reg-names = "dbi", "elbi", "config";
99        #address-cells = <3>;
100        #size-cells = <2>;
101        #interrupt-cells = <1>;
102        device_type = "pci";
103        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
104        clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
105        clock-names = "pcie", "pcie_bus";
106        phys = <&pcie_phy>;
107        pinctrl-0 = <&pcie_bus &pcie_wlanen>;
108        pinctrl-names = "default";
109        num-lanes = <1>;
110        num-viewport = <3>;
111        bus-range = <0x00 0xff>;
112        ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000>,
113                 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
114        vdd10-supply = <&ldo6_reg>;
115        vdd18-supply = <&ldo7_reg>;
116        interrupt-map-mask = <0 0 0 0>;
117        interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
118    };
119...
120