xref: /linux/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml (revision 9ff17e6bdaa50892dd9bdb1b116cb71b73dd711a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: DesignWare based PCIe controller on Rockchip SoCs
8
9maintainers:
10  - Shawn Lin <shawn.lin@rock-chips.com>
11  - Simon Xue <xxm@rock-chips.com>
12  - Heiko Stuebner <heiko@sntech.de>
13
14description: |+
15  RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16  PCIe IP and thus inherits all the common properties defined in
17  snps,dw-pcie.yaml.
18
19allOf:
20  - $ref: /schemas/pci/snps,dw-pcie.yaml#
21
22properties:
23  compatible:
24    oneOf:
25      - const: rockchip,rk3568-pcie
26      - items:
27          - enum:
28              - rockchip,rk3588-pcie
29          - const: rockchip,rk3568-pcie
30
31  reg:
32    items:
33      - description: Data Bus Interface (DBI) registers
34      - description: Rockchip designed configuration registers
35      - description: Config registers
36
37  reg-names:
38    items:
39      - const: dbi
40      - const: apb
41      - const: config
42
43  clocks:
44    items:
45      - description: AHB clock for PCIe master
46      - description: AHB clock for PCIe slave
47      - description: AHB clock for PCIe dbi
48      - description: APB clock for PCIe
49      - description: Auxiliary clock for PCIe
50
51  clock-names:
52    items:
53      - const: aclk_mst
54      - const: aclk_slv
55      - const: aclk_dbi
56      - const: pclk
57      - const: aux
58
59  msi-map: true
60
61  num-lanes: true
62
63  phys:
64    maxItems: 1
65
66  phy-names:
67    const: pcie-phy
68
69  power-domains:
70    maxItems: 1
71
72  ranges:
73    maxItems: 2
74
75  resets:
76    maxItems: 1
77
78  reset-names:
79    const: pipe
80
81  vpcie3v3-supply: true
82
83required:
84  - compatible
85  - reg
86  - reg-names
87  - clocks
88  - clock-names
89  - msi-map
90  - num-lanes
91  - phys
92  - phy-names
93  - power-domains
94  - resets
95  - reset-names
96
97unevaluatedProperties: false
98
99examples:
100  - |
101
102    bus {
103        #address-cells = <2>;
104        #size-cells = <2>;
105
106        pcie3x2: pcie@fe280000 {
107            compatible = "rockchip,rk3568-pcie";
108            reg = <0x3 0xc0800000 0x0 0x390000>,
109                  <0x0 0xfe280000 0x0 0x10000>,
110                  <0x3 0x80000000 0x0 0x100000>;
111            reg-names = "dbi", "apb", "config";
112            bus-range = <0x20 0x2f>;
113            clocks = <&cru 143>, <&cru 144>,
114                     <&cru 145>, <&cru 146>,
115                     <&cru 147>;
116            clock-names = "aclk_mst", "aclk_slv",
117                          "aclk_dbi", "pclk",
118                          "aux";
119            device_type = "pci";
120            linux,pci-domain = <2>;
121            max-link-speed = <2>;
122            msi-map = <0x2000 &its 0x2000 0x1000>;
123            num-lanes = <2>;
124            phys = <&pcie30phy>;
125            phy-names = "pcie-phy";
126            power-domains = <&power 15>;
127            ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
128                     <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
129            resets = <&cru 193>;
130            reset-names = "pipe";
131            #address-cells = <3>;
132            #size-cells = <2>;
133        };
134    };
135...
136