1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: DesignWare based PCIe controller on Rockchip SoCs 8 9maintainers: 10 - Shawn Lin <shawn.lin@rock-chips.com> 11 - Simon Xue <xxm@rock-chips.com> 12 - Heiko Stuebner <heiko@sntech.de> 13 14description: |+ 15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare 16 PCIe IP and thus inherits all the common properties defined in 17 snps,dw-pcie.yaml. 18 19allOf: 20 - $ref: /schemas/pci/snps,dw-pcie.yaml# 21 22properties: 23 compatible: 24 oneOf: 25 - const: rockchip,rk3568-pcie 26 - items: 27 - enum: 28 - rockchip,rk3588-pcie 29 - const: rockchip,rk3568-pcie 30 31 reg: 32 items: 33 - description: Data Bus Interface (DBI) registers 34 - description: Rockchip designed configuration registers 35 - description: Config registers 36 37 reg-names: 38 items: 39 - const: dbi 40 - const: apb 41 - const: config 42 43 clocks: 44 minItems: 5 45 items: 46 - description: AHB clock for PCIe master 47 - description: AHB clock for PCIe slave 48 - description: AHB clock for PCIe dbi 49 - description: APB clock for PCIe 50 - description: Auxiliary clock for PCIe 51 - description: PIPE clock 52 - description: Reference clock for PCIe 53 54 clock-names: 55 minItems: 5 56 items: 57 - const: aclk_mst 58 - const: aclk_slv 59 - const: aclk_dbi 60 - const: pclk 61 - const: aux 62 - const: pipe 63 - const: ref 64 65 interrupts: 66 items: 67 - description: 68 Combined system interrupt, which is used to signal the following 69 interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, 70 hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, 71 edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app 72 - description: 73 Combined PM interrupt, which is used to signal the following 74 interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, 75 linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, 76 linkst_out_l0s, pm_dstate_update 77 - description: 78 Combined message interrupt, which is used to signal the following 79 interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, 80 pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active 81 - description: 82 Combined legacy interrupt, which is used to signal the following 83 interrupts - inta, intb, intc, intd 84 - description: 85 Combined error interrupt, which is used to signal the following 86 interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, 87 tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, 88 nf_err_rx, f_err_rx, radm_qoverflow 89 90 interrupt-names: 91 items: 92 - const: sys 93 - const: pmc 94 - const: msg 95 - const: legacy 96 - const: err 97 98 legacy-interrupt-controller: 99 description: Interrupt controller node for handling legacy PCI interrupts. 100 type: object 101 additionalProperties: false 102 properties: 103 "#address-cells": 104 const: 0 105 106 "#interrupt-cells": 107 const: 1 108 109 interrupt-controller: true 110 111 interrupts: 112 items: 113 - description: combined legacy interrupt 114 required: 115 - "#address-cells" 116 - "#interrupt-cells" 117 - interrupt-controller 118 - interrupts 119 120 msi-map: true 121 122 num-lanes: true 123 124 phys: 125 maxItems: 1 126 127 phy-names: 128 const: pcie-phy 129 130 power-domains: 131 maxItems: 1 132 133 ranges: 134 minItems: 2 135 maxItems: 3 136 137 resets: 138 minItems: 1 139 maxItems: 2 140 141 reset-names: 142 oneOf: 143 - const: pipe 144 - items: 145 - const: pwr 146 - const: pipe 147 148 vpcie3v3-supply: true 149 150required: 151 - compatible 152 - reg 153 - reg-names 154 - clocks 155 - clock-names 156 - msi-map 157 - num-lanes 158 - phys 159 - phy-names 160 - power-domains 161 - resets 162 - reset-names 163 164unevaluatedProperties: false 165 166examples: 167 - | 168 #include <dt-bindings/interrupt-controller/arm-gic.h> 169 170 bus { 171 #address-cells = <2>; 172 #size-cells = <2>; 173 174 pcie3x2: pcie@fe280000 { 175 compatible = "rockchip,rk3568-pcie"; 176 reg = <0x3 0xc0800000 0x0 0x390000>, 177 <0x0 0xfe280000 0x0 0x10000>, 178 <0x3 0x80000000 0x0 0x100000>; 179 reg-names = "dbi", "apb", "config"; 180 bus-range = <0x20 0x2f>; 181 clocks = <&cru 143>, <&cru 144>, 182 <&cru 145>, <&cru 146>, 183 <&cru 147>; 184 clock-names = "aclk_mst", "aclk_slv", 185 "aclk_dbi", "pclk", 186 "aux"; 187 device_type = "pci"; 188 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 194 linux,pci-domain = <2>; 195 max-link-speed = <2>; 196 msi-map = <0x2000 &its 0x2000 0x1000>; 197 num-lanes = <2>; 198 phys = <&pcie30phy>; 199 phy-names = "pcie-phy"; 200 power-domains = <&power 15>; 201 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>, 202 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; 203 resets = <&cru 193>; 204 reset-names = "pipe"; 205 #address-cells = <3>; 206 #size-cells = <2>; 207 208 legacy-interrupt-controller { 209 interrupt-controller; 210 #address-cells = <0>; 211 #interrupt-cells = <1>; 212 interrupt-parent = <&gic>; 213 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 214 }; 215 }; 216 }; 217... 218