xref: /linux/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml (revision 3daee2e4b3568f0ed88b0598df96547fcf21cb9b) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip AXI PCIe Root Port Bridge Host
8
9maintainers:
10  - Shawn Lin <shawn.lin@rock-chips.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-host-bridge.yaml#
14  - $ref: rockchip,rk3399-pcie-common.yaml#
15
16properties:
17  compatible:
18    const: rockchip,rk3399-pcie
19
20  reg: true
21
22  reg-names:
23    items:
24      - const: axi-base
25      - const: apb-base
26
27  interrupts:
28    maxItems: 3
29
30  interrupt-names:
31    items:
32      - const: sys
33      - const: legacy
34      - const: client
35
36  aspm-no-l0s:
37    description: This property is needed if using 24MHz OSC for RC's PHY.
38
39  ep-gpios:
40    maxItems: 1
41    description: pre-reset GPIO
42
43  vpcie12v-supply:
44    description: The 12v regulator to use for PCIe.
45
46  vpcie3v3-supply:
47    description: The 3.3v regulator to use for PCIe.
48
49  vpcie1v8-supply:
50    description: The 1.8v regulator to use for PCIe.
51
52  vpcie0v9-supply:
53    description: The 0.9v regulator to use for PCIe.
54
55  interrupt-controller:
56    type: object
57    additionalProperties: false
58
59    properties:
60      '#address-cells':
61        const: 0
62
63      '#interrupt-cells':
64        const: 1
65
66      interrupt-controller: true
67
68required:
69  - ranges
70  - "#interrupt-cells"
71  - interrupts
72  - interrupt-controller
73  - interrupt-map
74  - interrupt-map-mask
75  - msi-map
76
77unevaluatedProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/gpio/gpio.h>
83    #include <dt-bindings/clock/rk3399-cru.h>
84
85    bus {
86        #address-cells = <2>;
87        #size-cells = <2>;
88
89        pcie@f8000000 {
90            compatible = "rockchip,rk3399-pcie";
91            device_type = "pci";
92            #address-cells = <3>;
93            #size-cells = <2>;
94            clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
95              <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
96            clock-names = "aclk", "aclk-perf",
97                    "hclk", "pm";
98            interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
99                  <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
100                  <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
101            interrupt-names = "sys", "legacy", "client";
102            ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
103            ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
104                0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
105            num-lanes = <4>;
106            msi-map = <0x0 &its 0x0 0x1000>;
107            reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
108            reg-names = "axi-base", "apb-base";
109            resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
110              <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
111              <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
112            reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
113                    "pm", "pclk", "aclk";
114            /* deprecated legacy PHY model */
115            phys = <&pcie_phy>;
116            phy-names = "pcie-phy";
117            pinctrl-names = "default";
118            pinctrl-0 = <&pcie_clkreq>;
119            #interrupt-cells = <1>;
120            interrupt-map-mask = <0 0 0 7>;
121            interrupt-map = <0 0 0 1 &pcie0_intc 0>,
122                <0 0 0 2 &pcie0_intc 1>,
123                <0 0 0 3 &pcie0_intc 2>,
124                <0 0 0 4 &pcie0_intc 3>;
125
126            pcie0_intc: interrupt-controller {
127                interrupt-controller;
128                #address-cells = <0>;
129                #interrupt-cells = <1>;
130            };
131        };
132    };
133...
134