1*aa222f93SRob Herring# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*aa222f93SRob Herring%YAML 1.2 3*aa222f93SRob Herring--- 4*aa222f93SRob Herring$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml# 5*aa222f93SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6*aa222f93SRob Herring 7*aa222f93SRob Herringtitle: Rockchip AXI PCIe Endpoint 8*aa222f93SRob Herring 9*aa222f93SRob Herringmaintainers: 10*aa222f93SRob Herring - Shawn Lin <shawn.lin@rock-chips.com> 11*aa222f93SRob Herring 12*aa222f93SRob HerringallOf: 13*aa222f93SRob Herring - $ref: /schemas/pci/pci-ep.yaml# 14*aa222f93SRob Herring - $ref: rockchip,rk3399-pcie-common.yaml# 15*aa222f93SRob Herring 16*aa222f93SRob Herringproperties: 17*aa222f93SRob Herring compatible: 18*aa222f93SRob Herring const: rockchip,rk3399-pcie-ep 19*aa222f93SRob Herring 20*aa222f93SRob Herring reg: true 21*aa222f93SRob Herring 22*aa222f93SRob Herring reg-names: 23*aa222f93SRob Herring items: 24*aa222f93SRob Herring - const: apb-base 25*aa222f93SRob Herring - const: mem-base 26*aa222f93SRob Herring 27*aa222f93SRob Herring rockchip,max-outbound-regions: 28*aa222f93SRob Herring description: Maximum number of outbound regions 29*aa222f93SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 30*aa222f93SRob Herring maximum: 32 31*aa222f93SRob Herring default: 32 32*aa222f93SRob Herring 33*aa222f93SRob Herringrequired: 34*aa222f93SRob Herring - rockchip,max-outbound-regions 35*aa222f93SRob Herring 36*aa222f93SRob HerringunevaluatedProperties: false 37*aa222f93SRob Herring 38*aa222f93SRob Herringexamples: 39*aa222f93SRob Herring - | 40*aa222f93SRob Herring #include <dt-bindings/interrupt-controller/arm-gic.h> 41*aa222f93SRob Herring #include <dt-bindings/gpio/gpio.h> 42*aa222f93SRob Herring #include <dt-bindings/clock/rk3399-cru.h> 43*aa222f93SRob Herring 44*aa222f93SRob Herring bus { 45*aa222f93SRob Herring #address-cells = <2>; 46*aa222f93SRob Herring #size-cells = <2>; 47*aa222f93SRob Herring 48*aa222f93SRob Herring pcie-ep@f8000000 { 49*aa222f93SRob Herring compatible = "rockchip,rk3399-pcie-ep"; 50*aa222f93SRob Herring reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; 51*aa222f93SRob Herring reg-names = "apb-base", "mem-base"; 52*aa222f93SRob Herring clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 53*aa222f93SRob Herring <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 54*aa222f93SRob Herring clock-names = "aclk", "aclk-perf", 55*aa222f93SRob Herring "hclk", "pm"; 56*aa222f93SRob Herring max-functions = /bits/ 8 <8>; 57*aa222f93SRob Herring num-lanes = <4>; 58*aa222f93SRob Herring resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 59*aa222f93SRob Herring <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , 60*aa222f93SRob Herring <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; 61*aa222f93SRob Herring reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 62*aa222f93SRob Herring "pm", "pclk", "aclk"; 63*aa222f93SRob Herring phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; 64*aa222f93SRob Herring phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; 65*aa222f93SRob Herring rockchip,max-outbound-regions = <16>; 66*aa222f93SRob Herring }; 67*aa222f93SRob Herring }; 68*aa222f93SRob Herring... 69