1aa222f93SRob Herring# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2aa222f93SRob Herring%YAML 1.2 3aa222f93SRob Herring--- 4aa222f93SRob Herring$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml# 5aa222f93SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6aa222f93SRob Herring 7aa222f93SRob Herringtitle: Rockchip AXI PCIe Endpoint 8aa222f93SRob Herring 9aa222f93SRob Herringmaintainers: 10aa222f93SRob Herring - Shawn Lin <shawn.lin@rock-chips.com> 11aa222f93SRob Herring 12aa222f93SRob HerringallOf: 13aa222f93SRob Herring - $ref: /schemas/pci/pci-ep.yaml# 14aa222f93SRob Herring - $ref: rockchip,rk3399-pcie-common.yaml# 15aa222f93SRob Herring 16aa222f93SRob Herringproperties: 17aa222f93SRob Herring compatible: 18aa222f93SRob Herring const: rockchip,rk3399-pcie-ep 19aa222f93SRob Herring 20aa222f93SRob Herring reg: true 21aa222f93SRob Herring 22aa222f93SRob Herring reg-names: 23aa222f93SRob Herring items: 24aa222f93SRob Herring - const: apb-base 25aa222f93SRob Herring - const: mem-base 26aa222f93SRob Herring 27aa222f93SRob Herring rockchip,max-outbound-regions: 28aa222f93SRob Herring description: Maximum number of outbound regions 29aa222f93SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 30aa222f93SRob Herring maximum: 32 31aa222f93SRob Herring default: 32 32aa222f93SRob Herring 33aa222f93SRob Herringrequired: 34aa222f93SRob Herring - rockchip,max-outbound-regions 35aa222f93SRob Herring 36aa222f93SRob HerringunevaluatedProperties: false 37aa222f93SRob Herring 38aa222f93SRob Herringexamples: 39aa222f93SRob Herring - | 40aa222f93SRob Herring #include <dt-bindings/interrupt-controller/arm-gic.h> 41aa222f93SRob Herring #include <dt-bindings/gpio/gpio.h> 42aa222f93SRob Herring #include <dt-bindings/clock/rk3399-cru.h> 43aa222f93SRob Herring 44aa222f93SRob Herring bus { 45aa222f93SRob Herring #address-cells = <2>; 46aa222f93SRob Herring #size-cells = <2>; 47aa222f93SRob Herring 48aa222f93SRob Herring pcie-ep@f8000000 { 49aa222f93SRob Herring compatible = "rockchip,rk3399-pcie-ep"; 50*21a2960dSRick Wertenbroek reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>; 51aa222f93SRob Herring reg-names = "apb-base", "mem-base"; 52aa222f93SRob Herring clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 53aa222f93SRob Herring <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 54aa222f93SRob Herring clock-names = "aclk", "aclk-perf", 55aa222f93SRob Herring "hclk", "pm"; 56aa222f93SRob Herring max-functions = /bits/ 8 <8>; 57aa222f93SRob Herring num-lanes = <4>; 58aa222f93SRob Herring resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 59aa222f93SRob Herring <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , 60aa222f93SRob Herring <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; 61aa222f93SRob Herring reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 62aa222f93SRob Herring "pm", "pclk", "aclk"; 63aa222f93SRob Herring phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; 64aa222f93SRob Herring phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; 65aa222f93SRob Herring rockchip,max-outbound-regions = <16>; 66*21a2960dSRick Wertenbroek pinctrl-names = "default"; 67*21a2960dSRick Wertenbroek pinctrl-0 = <&pcie_clkreqnb_cpm>; 68aa222f93SRob Herring }; 69aa222f93SRob Herring }; 70aa222f93SRob Herring... 71