1*409ae431SHerve Codina# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*409ae431SHerve Codina%YAML 1.2 3*409ae431SHerve Codina--- 4*409ae431SHerve Codina$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml# 5*409ae431SHerve Codina$schema: http://devicetree.org/meta-schemas/core.yaml# 6*409ae431SHerve Codina 7*409ae431SHerve Codinatitle: Renesas AHB to PCI bridge 8*409ae431SHerve Codina 9*409ae431SHerve Codinamaintainers: 10*409ae431SHerve Codina - Marek Vasut <marek.vasut+renesas@gmail.com> 11*409ae431SHerve Codina - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 12*409ae431SHerve Codina 13*409ae431SHerve Codinadescription: | 14*409ae431SHerve Codina This is the bridge used internally to connect the USB controllers to the 15*409ae431SHerve Codina AHB. There is one bridge instance per USB port connected to the internal 16*409ae431SHerve Codina OHCI and EHCI controllers. 17*409ae431SHerve Codina 18*409ae431SHerve CodinaallOf: 19*409ae431SHerve Codina - $ref: /schemas/pci/pci-bus.yaml# 20*409ae431SHerve Codina 21*409ae431SHerve Codinaproperties: 22*409ae431SHerve Codina compatible: 23*409ae431SHerve Codina oneOf: 24*409ae431SHerve Codina - items: 25*409ae431SHerve Codina - enum: 26*409ae431SHerve Codina - renesas,pci-r8a7742 # RZ/G1H 27*409ae431SHerve Codina - renesas,pci-r8a7743 # RZ/G1M 28*409ae431SHerve Codina - renesas,pci-r8a7744 # RZ/G1N 29*409ae431SHerve Codina - renesas,pci-r8a7745 # RZ/G1E 30*409ae431SHerve Codina - renesas,pci-r8a7790 # R-Car H2 31*409ae431SHerve Codina - renesas,pci-r8a7791 # R-Car M2-W 32*409ae431SHerve Codina - renesas,pci-r8a7793 # R-Car M2-N 33*409ae431SHerve Codina - renesas,pci-r8a7794 # R-Car E2 34*409ae431SHerve Codina - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 35*409ae431SHerve Codina 36*409ae431SHerve Codina reg: 37*409ae431SHerve Codina items: 38*409ae431SHerve Codina - description: Operational registers for the OHCI/EHCI controllers. 39*409ae431SHerve Codina - description: Bridge configuration and control registers. 40*409ae431SHerve Codina 41*409ae431SHerve Codina interrupts: 42*409ae431SHerve Codina maxItems: 1 43*409ae431SHerve Codina 44*409ae431SHerve Codina clocks: 45*409ae431SHerve Codina items: 46*409ae431SHerve Codina - description: Device clock 47*409ae431SHerve Codina 48*409ae431SHerve Codina clock-names: 49*409ae431SHerve Codina items: 50*409ae431SHerve Codina - const: pclk 51*409ae431SHerve Codina 52*409ae431SHerve Codina resets: 53*409ae431SHerve Codina maxItems: 1 54*409ae431SHerve Codina 55*409ae431SHerve Codina power-domains: 56*409ae431SHerve Codina maxItems: 1 57*409ae431SHerve Codina 58*409ae431SHerve Codina bus-range: 59*409ae431SHerve Codina description: | 60*409ae431SHerve Codina The PCI bus number range; as this is a single bus, the range 61*409ae431SHerve Codina should be specified as the same value twice. 62*409ae431SHerve Codina 63*409ae431SHerve Codina dma-ranges: 64*409ae431SHerve Codina description: | 65*409ae431SHerve Codina A single range for the inbound memory region. If not supplied, 66*409ae431SHerve Codina defaults to 1GiB at 0x40000000. Note there are hardware restrictions on 67*409ae431SHerve Codina the allowed combinations of address and size. 68*409ae431SHerve Codina maxItems: 1 69*409ae431SHerve Codina 70*409ae431SHerve CodinapatternProperties: 71*409ae431SHerve Codina 'usb@[0-1],0': 72*409ae431SHerve Codina type: object 73*409ae431SHerve Codina 74*409ae431SHerve Codina description: 75*409ae431SHerve Codina This a USB controller PCI device 76*409ae431SHerve Codina 77*409ae431SHerve Codina properties: 78*409ae431SHerve Codina reg: 79*409ae431SHerve Codina description: 80*409ae431SHerve Codina Identify the correct bus, device and function number in the 81*409ae431SHerve Codina form <bdf 0 0 0 0>. 82*409ae431SHerve Codina 83*409ae431SHerve Codina items: 84*409ae431SHerve Codina minItems: 5 85*409ae431SHerve Codina maxItems: 5 86*409ae431SHerve Codina 87*409ae431SHerve Codina phys: 88*409ae431SHerve Codina description: 89*409ae431SHerve Codina Reference to the USB phy 90*409ae431SHerve Codina maxItems: 1 91*409ae431SHerve Codina 92*409ae431SHerve Codina phy-names: 93*409ae431SHerve Codina maxItems: 1 94*409ae431SHerve Codina 95*409ae431SHerve Codina required: 96*409ae431SHerve Codina - reg 97*409ae431SHerve Codina - phys 98*409ae431SHerve Codina - phy-names 99*409ae431SHerve Codina 100*409ae431SHerve Codina unevaluatedProperties: false 101*409ae431SHerve Codina 102*409ae431SHerve Codinarequired: 103*409ae431SHerve Codina - compatible 104*409ae431SHerve Codina - reg 105*409ae431SHerve Codina - interrupts 106*409ae431SHerve Codina - interrupt-map 107*409ae431SHerve Codina - interrupt-map-mask 108*409ae431SHerve Codina - clocks 109*409ae431SHerve Codina - resets 110*409ae431SHerve Codina - power-domains 111*409ae431SHerve Codina - bus-range 112*409ae431SHerve Codina - "#address-cells" 113*409ae431SHerve Codina - "#size-cells" 114*409ae431SHerve Codina - "#interrupt-cells" 115*409ae431SHerve Codina 116*409ae431SHerve CodinaunevaluatedProperties: false 117*409ae431SHerve Codina 118*409ae431SHerve Codinaexamples: 119*409ae431SHerve Codina - | 120*409ae431SHerve Codina #include <dt-bindings/interrupt-controller/arm-gic.h> 121*409ae431SHerve Codina #include <dt-bindings/clock/r8a7790-cpg-mssr.h> 122*409ae431SHerve Codina #include <dt-bindings/power/r8a7790-sysc.h> 123*409ae431SHerve Codina 124*409ae431SHerve Codina pci@ee090000 { 125*409ae431SHerve Codina compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; 126*409ae431SHerve Codina device_type = "pci"; 127*409ae431SHerve Codina reg = <0xee090000 0xc00>, 128*409ae431SHerve Codina <0xee080000 0x1100>; 129*409ae431SHerve Codina clocks = <&cpg CPG_MOD 703>; 130*409ae431SHerve Codina power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 131*409ae431SHerve Codina resets = <&cpg 703>; 132*409ae431SHerve Codina interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 133*409ae431SHerve Codina 134*409ae431SHerve Codina bus-range = <0 0>; 135*409ae431SHerve Codina #address-cells = <3>; 136*409ae431SHerve Codina #size-cells = <2>; 137*409ae431SHerve Codina #interrupt-cells = <1>; 138*409ae431SHerve Codina ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>; 139*409ae431SHerve Codina dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>; 140*409ae431SHerve Codina interrupt-map-mask = <0xf800 0 0 0x7>; 141*409ae431SHerve Codina interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 142*409ae431SHerve Codina <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 143*409ae431SHerve Codina <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 144*409ae431SHerve Codina 145*409ae431SHerve Codina usb@1,0 { 146*409ae431SHerve Codina reg = <0x800 0 0 0 0>; 147*409ae431SHerve Codina phys = <&usb0 0>; 148*409ae431SHerve Codina phy-names = "usb"; 149*409ae431SHerve Codina }; 150*409ae431SHerve Codina 151*409ae431SHerve Codina usb@2,0 { 152*409ae431SHerve Codina reg = <0x1000 0 0 0 0>; 153*409ae431SHerve Codina phys = <&usb0 0>; 154*409ae431SHerve Codina phy-names = "usb"; 155*409ae431SHerve Codina }; 156*409ae431SHerve Codina }; 157