xref: /linux/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml (revision 0c8ea05e9b3d8e5287e2a968f2a2e744dfd31b99) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022-2023 Renesas Electronics Corp.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Renesas R-Car Gen4 PCIe Host
9
10maintainers:
11  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
12
13allOf:
14  - $ref: snps,dw-pcie.yaml#
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - renesas,r8a779f0-pcie      # R-Car S4-8
21          - renesas,r8a779g0-pcie      # R-Car V4H
22      - const: renesas,rcar-gen4-pcie  # R-Car Gen4
23
24  reg:
25    maxItems: 7
26
27  reg-names:
28    items:
29      - const: dbi
30      - const: dbi2
31      - const: atu
32      - const: dma
33      - const: app
34      - const: phy
35      - const: config
36
37  interrupts:
38    maxItems: 4
39
40  interrupt-names:
41    items:
42      - const: msi
43      - const: dma
44      - const: sft_ce
45      - const: app
46
47  clocks:
48    maxItems: 2
49
50  clock-names:
51    items:
52      - const: core
53      - const: ref
54
55  power-domains:
56    maxItems: 1
57
58  resets:
59    maxItems: 1
60
61  reset-names:
62    items:
63      - const: pwr
64
65  max-link-speed:
66    maximum: 4
67
68  num-lanes:
69    maximum: 4
70
71required:
72  - compatible
73  - reg
74  - reg-names
75  - interrupts
76  - interrupt-names
77  - clocks
78  - clock-names
79  - power-domains
80  - resets
81  - reset-names
82
83unevaluatedProperties: false
84
85examples:
86  - |
87    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
88    #include <dt-bindings/interrupt-controller/arm-gic.h>
89    #include <dt-bindings/power/r8a779f0-sysc.h>
90
91    soc {
92        #address-cells = <2>;
93        #size-cells = <2>;
94
95        pcie: pcie@e65d0000 {
96            compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
97            reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
98                  <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
99                  <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
100                  <0 0xfe000000 0 0x400000>;
101            reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
102            interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
103                         <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
104                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
105                         <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
106            interrupt-names = "msi", "dma", "sft_ce", "app";
107            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
108            clock-names = "core", "ref";
109            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
110            resets = <&cpg 624>;
111            reset-names = "pwr";
112            max-link-speed = <4>;
113            num-lanes = <2>;
114            #address-cells = <3>;
115            #size-cells = <2>;
116            bus-range = <0x00 0xff>;
117            device_type = "pci";
118            ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
119                     <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
120            dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
121            #interrupt-cells = <1>;
122            interrupt-map-mask = <0 0 0 7>;
123            interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
124                            <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
125                            <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
126                            <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
127            snps,enable-cdm-check;
128        };
129    };
130