1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm PCI express root complex 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 12 13description: | 14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare 15 PCIe IP. 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - qcom,pcie-apq8064 22 - qcom,pcie-apq8084 23 - qcom,pcie-ipq4019 24 - qcom,pcie-ipq6018 25 - qcom,pcie-ipq8064 26 - qcom,pcie-ipq8064-v2 27 - qcom,pcie-ipq8074 28 - qcom,pcie-ipq8074-gen3 29 - qcom,pcie-msm8996 30 - qcom,pcie-qcs404 31 - qcom,pcie-sdm845 32 - qcom,pcie-sdx55 33 - items: 34 - const: qcom,pcie-msm8998 35 - const: qcom,pcie-msm8996 36 37 reg: 38 minItems: 4 39 maxItems: 6 40 41 reg-names: 42 minItems: 4 43 maxItems: 6 44 45 interrupts: 46 minItems: 1 47 maxItems: 8 48 49 interrupt-names: 50 minItems: 1 51 maxItems: 8 52 53 iommu-map: 54 minItems: 1 55 maxItems: 16 56 57 # Common definitions for clocks, clock-names and reset. 58 # Platform constraints are described later. 59 clocks: 60 minItems: 3 61 maxItems: 13 62 63 clock-names: 64 minItems: 3 65 maxItems: 13 66 67 dma-coherent: true 68 69 interconnects: 70 maxItems: 2 71 72 interconnect-names: 73 items: 74 - const: pcie-mem 75 - const: cpu-pcie 76 77 resets: 78 minItems: 1 79 maxItems: 12 80 81 reset-names: 82 minItems: 1 83 maxItems: 12 84 85 vdda-supply: 86 description: A phandle to the core analog power supply 87 88 vdda_phy-supply: 89 description: A phandle to the core analog power supply for PHY 90 91 vdda_refclk-supply: 92 description: A phandle to the core analog power supply for IC which generates reference clock 93 94 vddpe-3v3-supply: 95 description: A phandle to the PCIe endpoint power supply 96 97 phys: 98 maxItems: 1 99 100 phy-names: 101 items: 102 - const: pciephy 103 104 power-domains: 105 maxItems: 1 106 107 perst-gpios: 108 description: GPIO controlled connection to PERST# signal 109 maxItems: 1 110 111 required-opps: 112 maxItems: 1 113 114 wake-gpios: 115 description: GPIO controlled connection to WAKE# signal 116 maxItems: 1 117 118required: 119 - compatible 120 - reg 121 - reg-names 122 - interrupt-map-mask 123 - interrupt-map 124 - clocks 125 - clock-names 126 127anyOf: 128 - required: 129 - interrupts 130 - interrupt-names 131 - "#interrupt-cells" 132 - required: 133 - msi-map 134 135allOf: 136 - $ref: /schemas/pci/pci-host-bridge.yaml# 137 - if: 138 properties: 139 compatible: 140 contains: 141 enum: 142 - qcom,pcie-apq8064 143 - qcom,pcie-ipq4019 144 - qcom,pcie-ipq8064 145 - qcom,pcie-ipq8064v2 146 - qcom,pcie-ipq8074 147 - qcom,pcie-qcs404 148 then: 149 properties: 150 reg: 151 minItems: 4 152 maxItems: 4 153 reg-names: 154 items: 155 - const: dbi # DesignWare PCIe registers 156 - const: elbi # External local bus interface registers 157 - const: parf # Qualcomm specific registers 158 - const: config # PCIe configuration space 159 160 - if: 161 properties: 162 compatible: 163 contains: 164 enum: 165 - qcom,pcie-ipq6018 166 - qcom,pcie-ipq8074-gen3 167 then: 168 properties: 169 reg: 170 minItems: 5 171 maxItems: 5 172 reg-names: 173 items: 174 - const: dbi # DesignWare PCIe registers 175 - const: elbi # External local bus interface registers 176 - const: atu # ATU address space 177 - const: parf # Qualcomm specific registers 178 - const: config # PCIe configuration space 179 180 - if: 181 properties: 182 compatible: 183 contains: 184 enum: 185 - qcom,pcie-apq8084 186 - qcom,pcie-msm8996 187 - qcom,pcie-sdm845 188 then: 189 properties: 190 reg: 191 minItems: 4 192 maxItems: 5 193 reg-names: 194 minItems: 4 195 items: 196 - const: parf # Qualcomm specific registers 197 - const: dbi # DesignWare PCIe registers 198 - const: elbi # External local bus interface registers 199 - const: config # PCIe configuration space 200 - const: mhi # MHI registers 201 202 - if: 203 properties: 204 compatible: 205 contains: 206 enum: 207 - qcom,pcie-sdx55 208 then: 209 properties: 210 reg: 211 minItems: 5 212 maxItems: 6 213 reg-names: 214 minItems: 5 215 items: 216 - const: parf # Qualcomm specific registers 217 - const: dbi # DesignWare PCIe registers 218 - const: elbi # External local bus interface registers 219 - const: atu # ATU address space 220 - const: config # PCIe configuration space 221 - const: mhi # MHI registers 222 223 - if: 224 properties: 225 compatible: 226 contains: 227 enum: 228 - qcom,pcie-apq8064 229 - qcom,pcie-ipq8064 230 - qcom,pcie-ipq8064v2 231 then: 232 properties: 233 clocks: 234 minItems: 3 235 maxItems: 5 236 clock-names: 237 minItems: 3 238 items: 239 - const: core # Clocks the pcie hw block 240 - const: iface # Configuration AHB clock 241 - const: phy # Clocks the pcie PHY block 242 - const: aux # Clocks the pcie AUX block, not on apq8064 243 - const: ref # Clocks the pcie ref block, not on apq8064 244 resets: 245 minItems: 5 246 maxItems: 6 247 reset-names: 248 minItems: 5 249 items: 250 - const: axi # AXI reset 251 - const: ahb # AHB reset 252 - const: por # POR reset 253 - const: pci # PCI reset 254 - const: phy # PHY reset 255 - const: ext # EXT reset, not on apq8064 256 required: 257 - vdda-supply 258 - vdda_phy-supply 259 - vdda_refclk-supply 260 261 - if: 262 properties: 263 compatible: 264 contains: 265 enum: 266 - qcom,pcie-apq8084 267 then: 268 properties: 269 clocks: 270 minItems: 4 271 maxItems: 4 272 clock-names: 273 items: 274 - const: iface # Configuration AHB clock 275 - const: master_bus # Master AXI clock 276 - const: slave_bus # Slave AXI clock 277 - const: aux # Auxiliary (AUX) clock 278 resets: 279 maxItems: 1 280 reset-names: 281 items: 282 - const: core # Core reset 283 284 - if: 285 properties: 286 compatible: 287 contains: 288 enum: 289 - qcom,pcie-ipq4019 290 then: 291 properties: 292 clocks: 293 minItems: 3 294 maxItems: 3 295 clock-names: 296 items: 297 - const: aux # Auxiliary (AUX) clock 298 - const: master_bus # Master AXI clock 299 - const: slave_bus # Slave AXI clock 300 resets: 301 minItems: 12 302 maxItems: 12 303 reset-names: 304 items: 305 - const: axi_m # AXI master reset 306 - const: axi_s # AXI slave reset 307 - const: pipe # PIPE reset 308 - const: axi_m_vmid # VMID reset 309 - const: axi_s_xpu # XPU reset 310 - const: parf # PARF reset 311 - const: phy # PHY reset 312 - const: axi_m_sticky # AXI sticky reset 313 - const: pipe_sticky # PIPE sticky reset 314 - const: pwr # PWR reset 315 - const: ahb # AHB reset 316 - const: phy_ahb # PHY AHB reset 317 318 - if: 319 properties: 320 compatible: 321 contains: 322 enum: 323 - qcom,pcie-msm8996 324 then: 325 properties: 326 clocks: 327 minItems: 5 328 maxItems: 5 329 clock-names: 330 items: 331 - const: pipe # Pipe Clock driving internal logic 332 - const: aux # Auxiliary (AUX) clock 333 - const: cfg # Configuration clock 334 - const: bus_master # Master AXI clock 335 - const: bus_slave # Slave AXI clock 336 resets: false 337 reset-names: false 338 339 - if: 340 properties: 341 compatible: 342 contains: 343 enum: 344 - qcom,pcie-ipq8074 345 then: 346 properties: 347 clocks: 348 minItems: 5 349 maxItems: 5 350 clock-names: 351 items: 352 - const: iface # PCIe to SysNOC BIU clock 353 - const: axi_m # AXI Master clock 354 - const: axi_s # AXI Slave clock 355 - const: ahb # AHB clock 356 - const: aux # Auxiliary clock 357 resets: 358 minItems: 7 359 maxItems: 7 360 reset-names: 361 items: 362 - const: pipe # PIPE reset 363 - const: sleep # Sleep reset 364 - const: sticky # Core Sticky reset 365 - const: axi_m # AXI Master reset 366 - const: axi_s # AXI Slave reset 367 - const: ahb # AHB Reset 368 - const: axi_m_sticky # AXI Master Sticky reset 369 370 - if: 371 properties: 372 compatible: 373 contains: 374 enum: 375 - qcom,pcie-ipq6018 376 - qcom,pcie-ipq8074-gen3 377 then: 378 properties: 379 clocks: 380 minItems: 5 381 maxItems: 5 382 clock-names: 383 items: 384 - const: iface # PCIe to SysNOC BIU clock 385 - const: axi_m # AXI Master clock 386 - const: axi_s # AXI Slave clock 387 - const: axi_bridge # AXI bridge clock 388 - const: rchng 389 resets: 390 minItems: 8 391 maxItems: 8 392 reset-names: 393 items: 394 - const: pipe # PIPE reset 395 - const: sleep # Sleep reset 396 - const: sticky # Core Sticky reset 397 - const: axi_m # AXI Master reset 398 - const: axi_s # AXI Slave reset 399 - const: ahb # AHB Reset 400 - const: axi_m_sticky # AXI Master Sticky reset 401 - const: axi_s_sticky # AXI Slave Sticky reset 402 403 - if: 404 properties: 405 compatible: 406 contains: 407 enum: 408 - qcom,pcie-qcs404 409 then: 410 properties: 411 clocks: 412 minItems: 4 413 maxItems: 4 414 clock-names: 415 items: 416 - const: iface # AHB clock 417 - const: aux # Auxiliary clock 418 - const: master_bus # AXI Master clock 419 - const: slave_bus # AXI Slave clock 420 resets: 421 minItems: 6 422 maxItems: 6 423 reset-names: 424 items: 425 - const: axi_m # AXI Master reset 426 - const: axi_s # AXI Slave reset 427 - const: axi_m_sticky # AXI Master Sticky reset 428 - const: pipe_sticky # PIPE sticky reset 429 - const: pwr # PWR reset 430 - const: ahb # AHB reset 431 432 - if: 433 properties: 434 compatible: 435 contains: 436 enum: 437 - qcom,pcie-sdm845 438 then: 439 oneOf: 440 # Unfortunately the "optional" ref clock is used in the middle of the list 441 - properties: 442 clocks: 443 minItems: 8 444 maxItems: 8 445 clock-names: 446 items: 447 - const: pipe # PIPE clock 448 - const: aux # Auxiliary clock 449 - const: cfg # Configuration clock 450 - const: bus_master # Master AXI clock 451 - const: bus_slave # Slave AXI clock 452 - const: slave_q2a # Slave Q2A clock 453 - const: ref # REFERENCE clock 454 - const: tbu # PCIe TBU clock 455 - properties: 456 clocks: 457 minItems: 7 458 maxItems: 7 459 clock-names: 460 items: 461 - const: pipe # PIPE clock 462 - const: aux # Auxiliary clock 463 - const: cfg # Configuration clock 464 - const: bus_master # Master AXI clock 465 - const: bus_slave # Slave AXI clock 466 - const: slave_q2a # Slave Q2A clock 467 - const: tbu # PCIe TBU clock 468 properties: 469 resets: 470 maxItems: 1 471 reset-names: 472 items: 473 - const: pci # PCIe core reset 474 475 - if: 476 properties: 477 compatible: 478 contains: 479 enum: 480 - qcom,pcie-sdx55 481 then: 482 properties: 483 clocks: 484 minItems: 7 485 maxItems: 7 486 clock-names: 487 items: 488 - const: pipe # PIPE clock 489 - const: aux # Auxiliary clock 490 - const: cfg # Configuration clock 491 - const: bus_master # Master AXI clock 492 - const: bus_slave # Slave AXI clock 493 - const: slave_q2a # Slave Q2A clock 494 - const: sleep # PCIe Sleep clock 495 resets: 496 maxItems: 1 497 reset-names: 498 items: 499 - const: pci # PCIe core reset 500 501 - if: 502 not: 503 properties: 504 compatible: 505 contains: 506 enum: 507 - qcom,pcie-apq8064 508 - qcom,pcie-ipq4019 509 - qcom,pcie-ipq8064 510 - qcom,pcie-ipq8064v2 511 - qcom,pcie-ipq8074 512 - qcom,pcie-ipq8074-gen3 513 - qcom,pcie-qcs404 514 then: 515 required: 516 - power-domains 517 518 - if: 519 not: 520 properties: 521 compatible: 522 contains: 523 enum: 524 - qcom,pcie-msm8996 525 then: 526 required: 527 - resets 528 - reset-names 529 530 - if: 531 properties: 532 compatible: 533 contains: 534 enum: 535 - qcom,pcie-msm8996 536 - qcom,pcie-sdm845 537 then: 538 oneOf: 539 - properties: 540 interrupts: 541 maxItems: 1 542 interrupt-names: 543 items: 544 - const: msi 545 - properties: 546 interrupts: 547 minItems: 8 548 interrupt-names: 549 items: 550 - const: msi0 551 - const: msi1 552 - const: msi2 553 - const: msi3 554 - const: msi4 555 - const: msi5 556 - const: msi6 557 - const: msi7 558 559 - if: 560 properties: 561 compatible: 562 contains: 563 enum: 564 - qcom,pcie-apq8064 565 - qcom,pcie-apq8084 566 - qcom,pcie-ipq4019 567 - qcom,pcie-ipq6018 568 - qcom,pcie-ipq8064 569 - qcom,pcie-ipq8064-v2 570 - qcom,pcie-ipq8074 571 - qcom,pcie-ipq8074-gen3 572 - qcom,pcie-qcs404 573 then: 574 properties: 575 interrupts: 576 maxItems: 1 577 interrupt-names: 578 items: 579 - const: msi 580 581unevaluatedProperties: false 582 583examples: 584 - | 585 #include <dt-bindings/interrupt-controller/arm-gic.h> 586 pcie@1b500000 { 587 compatible = "qcom,pcie-ipq8064"; 588 reg = <0x1b500000 0x1000>, 589 <0x1b502000 0x80>, 590 <0x1b600000 0x100>, 591 <0x0ff00000 0x100000>; 592 reg-names = "dbi", "elbi", "parf", "config"; 593 device_type = "pci"; 594 linux,pci-domain = <0>; 595 bus-range = <0x00 0xff>; 596 num-lanes = <1>; 597 #address-cells = <3>; 598 #size-cells = <2>; 599 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, 600 <0x82000000 0 0 0x08000000 0 0x07e00000>; 601 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-names = "msi"; 603 #interrupt-cells = <1>; 604 interrupt-map-mask = <0 0 0 0x7>; 605 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, 606 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, 607 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, 608 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&gcc 41>, 610 <&gcc 43>, 611 <&gcc 44>, 612 <&gcc 42>, 613 <&gcc 248>; 614 clock-names = "core", "iface", "phy", "aux", "ref"; 615 resets = <&gcc 27>, 616 <&gcc 26>, 617 <&gcc 25>, 618 <&gcc 24>, 619 <&gcc 23>, 620 <&gcc 22>; 621 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 622 pinctrl-0 = <&pcie_pins_default>; 623 pinctrl-names = "default"; 624 vdda-supply = <&pm8921_s3>; 625 vdda_phy-supply = <&pm8921_lvs6>; 626 vdda_refclk-supply = <&ext_3p3v>; 627 }; 628 - | 629 #include <dt-bindings/interrupt-controller/arm-gic.h> 630 #include <dt-bindings/gpio/gpio.h> 631 pcie@fc520000 { 632 compatible = "qcom,pcie-apq8084"; 633 reg = <0xfc520000 0x2000>, 634 <0xff000000 0x1000>, 635 <0xff001000 0x1000>, 636 <0xff002000 0x2000>; 637 reg-names = "parf", "dbi", "elbi", "config"; 638 device_type = "pci"; 639 linux,pci-domain = <0>; 640 bus-range = <0x00 0xff>; 641 num-lanes = <1>; 642 #address-cells = <3>; 643 #size-cells = <2>; 644 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>, 645 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; 646 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "msi"; 648 #interrupt-cells = <1>; 649 interrupt-map-mask = <0 0 0 0x7>; 650 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, 651 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, 652 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, 653 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&gcc 324>, 655 <&gcc 325>, 656 <&gcc 327>, 657 <&gcc 323>; 658 clock-names = "iface", "master_bus", "slave_bus", "aux"; 659 resets = <&gcc 81>; 660 reset-names = "core"; 661 power-domains = <&gcc 1>; 662 vdda-supply = <&pma8084_l3>; 663 phys = <&pciephy0>; 664 phy-names = "pciephy"; 665 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; 666 pinctrl-0 = <&pcie0_pins_default>; 667 pinctrl-names = "default"; 668 }; 669... 670