1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm PCI express root complex 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 12 13description: | 14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare 15 PCIe IP. 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - qcom,pcie-apq8064 22 - qcom,pcie-apq8084 23 - qcom,pcie-ipq4019 24 - qcom,pcie-ipq6018 25 - qcom,pcie-ipq8064 26 - qcom,pcie-ipq8064-v2 27 - qcom,pcie-ipq8074 28 - qcom,pcie-ipq8074-gen3 29 - qcom,pcie-msm8996 30 - qcom,pcie-qcs404 31 - qcom,pcie-sdm845 32 - qcom,pcie-sdx55 33 - items: 34 - const: qcom,pcie-msm8998 35 - const: qcom,pcie-msm8996 36 37 reg: 38 minItems: 4 39 maxItems: 6 40 41 reg-names: 42 minItems: 4 43 maxItems: 6 44 45 interrupts: 46 minItems: 1 47 maxItems: 8 48 49 interrupt-names: 50 minItems: 1 51 maxItems: 8 52 53 iommu-map: 54 minItems: 1 55 maxItems: 16 56 57 # Common definitions for clocks, clock-names and reset. 58 # Platform constraints are described later. 59 clocks: 60 minItems: 3 61 maxItems: 13 62 63 clock-names: 64 minItems: 3 65 maxItems: 13 66 67 dma-coherent: true 68 69 interconnects: 70 maxItems: 2 71 72 interconnect-names: 73 items: 74 - const: pcie-mem 75 - const: cpu-pcie 76 77 resets: 78 minItems: 1 79 maxItems: 12 80 81 reset-names: 82 minItems: 1 83 maxItems: 12 84 85 vdda-supply: 86 description: A phandle to the core analog power supply 87 88 vdda_phy-supply: 89 description: A phandle to the core analog power supply for PHY 90 91 vdda_refclk-supply: 92 description: A phandle to the core analog power supply for IC which generates reference clock 93 94 phys: 95 maxItems: 1 96 97 phy-names: 98 items: 99 - const: pciephy 100 101 power-domains: 102 maxItems: 1 103 104 perst-gpios: 105 description: GPIO controlled connection to PERST# signal 106 maxItems: 1 107 108 required-opps: 109 maxItems: 1 110 111 wake-gpios: 112 description: GPIO controlled connection to WAKE# signal 113 maxItems: 1 114 115required: 116 - compatible 117 - reg 118 - reg-names 119 - interrupt-map-mask 120 - interrupt-map 121 - clocks 122 - clock-names 123 124anyOf: 125 - required: 126 - interrupts 127 - interrupt-names 128 - "#interrupt-cells" 129 - required: 130 - msi-map 131 132allOf: 133 - $ref: /schemas/pci/pci-bus.yaml# 134 - if: 135 properties: 136 compatible: 137 contains: 138 enum: 139 - qcom,pcie-apq8064 140 - qcom,pcie-ipq4019 141 - qcom,pcie-ipq8064 142 - qcom,pcie-ipq8064v2 143 - qcom,pcie-ipq8074 144 - qcom,pcie-qcs404 145 then: 146 properties: 147 reg: 148 minItems: 4 149 maxItems: 4 150 reg-names: 151 items: 152 - const: dbi # DesignWare PCIe registers 153 - const: elbi # External local bus interface registers 154 - const: parf # Qualcomm specific registers 155 - const: config # PCIe configuration space 156 157 - if: 158 properties: 159 compatible: 160 contains: 161 enum: 162 - qcom,pcie-ipq6018 163 - qcom,pcie-ipq8074-gen3 164 then: 165 properties: 166 reg: 167 minItems: 5 168 maxItems: 5 169 reg-names: 170 items: 171 - const: dbi # DesignWare PCIe registers 172 - const: elbi # External local bus interface registers 173 - const: atu # ATU address space 174 - const: parf # Qualcomm specific registers 175 - const: config # PCIe configuration space 176 177 - if: 178 properties: 179 compatible: 180 contains: 181 enum: 182 - qcom,pcie-apq8084 183 - qcom,pcie-msm8996 184 - qcom,pcie-sdm845 185 then: 186 properties: 187 reg: 188 minItems: 4 189 maxItems: 5 190 reg-names: 191 minItems: 4 192 items: 193 - const: parf # Qualcomm specific registers 194 - const: dbi # DesignWare PCIe registers 195 - const: elbi # External local bus interface registers 196 - const: config # PCIe configuration space 197 - const: mhi # MHI registers 198 199 - if: 200 properties: 201 compatible: 202 contains: 203 enum: 204 - qcom,pcie-sdx55 205 then: 206 properties: 207 reg: 208 minItems: 5 209 maxItems: 6 210 reg-names: 211 minItems: 5 212 items: 213 - const: parf # Qualcomm specific registers 214 - const: dbi # DesignWare PCIe registers 215 - const: elbi # External local bus interface registers 216 - const: atu # ATU address space 217 - const: config # PCIe configuration space 218 - const: mhi # MHI registers 219 220 - if: 221 properties: 222 compatible: 223 contains: 224 enum: 225 - qcom,pcie-apq8064 226 - qcom,pcie-ipq8064 227 - qcom,pcie-ipq8064v2 228 then: 229 properties: 230 clocks: 231 minItems: 3 232 maxItems: 5 233 clock-names: 234 minItems: 3 235 items: 236 - const: core # Clocks the pcie hw block 237 - const: iface # Configuration AHB clock 238 - const: phy # Clocks the pcie PHY block 239 - const: aux # Clocks the pcie AUX block, not on apq8064 240 - const: ref # Clocks the pcie ref block, not on apq8064 241 resets: 242 minItems: 5 243 maxItems: 6 244 reset-names: 245 minItems: 5 246 items: 247 - const: axi # AXI reset 248 - const: ahb # AHB reset 249 - const: por # POR reset 250 - const: pci # PCI reset 251 - const: phy # PHY reset 252 - const: ext # EXT reset, not on apq8064 253 required: 254 - vdda-supply 255 - vdda_phy-supply 256 - vdda_refclk-supply 257 258 - if: 259 properties: 260 compatible: 261 contains: 262 enum: 263 - qcom,pcie-apq8084 264 then: 265 properties: 266 clocks: 267 minItems: 4 268 maxItems: 4 269 clock-names: 270 items: 271 - const: iface # Configuration AHB clock 272 - const: master_bus # Master AXI clock 273 - const: slave_bus # Slave AXI clock 274 - const: aux # Auxiliary (AUX) clock 275 resets: 276 maxItems: 1 277 reset-names: 278 items: 279 - const: core # Core reset 280 281 - if: 282 properties: 283 compatible: 284 contains: 285 enum: 286 - qcom,pcie-ipq4019 287 then: 288 properties: 289 clocks: 290 minItems: 3 291 maxItems: 3 292 clock-names: 293 items: 294 - const: aux # Auxiliary (AUX) clock 295 - const: master_bus # Master AXI clock 296 - const: slave_bus # Slave AXI clock 297 resets: 298 minItems: 12 299 maxItems: 12 300 reset-names: 301 items: 302 - const: axi_m # AXI master reset 303 - const: axi_s # AXI slave reset 304 - const: pipe # PIPE reset 305 - const: axi_m_vmid # VMID reset 306 - const: axi_s_xpu # XPU reset 307 - const: parf # PARF reset 308 - const: phy # PHY reset 309 - const: axi_m_sticky # AXI sticky reset 310 - const: pipe_sticky # PIPE sticky reset 311 - const: pwr # PWR reset 312 - const: ahb # AHB reset 313 - const: phy_ahb # PHY AHB reset 314 315 - if: 316 properties: 317 compatible: 318 contains: 319 enum: 320 - qcom,pcie-msm8996 321 then: 322 properties: 323 clocks: 324 minItems: 5 325 maxItems: 5 326 clock-names: 327 items: 328 - const: pipe # Pipe Clock driving internal logic 329 - const: aux # Auxiliary (AUX) clock 330 - const: cfg # Configuration clock 331 - const: bus_master # Master AXI clock 332 - const: bus_slave # Slave AXI clock 333 resets: false 334 reset-names: false 335 336 - if: 337 properties: 338 compatible: 339 contains: 340 enum: 341 - qcom,pcie-ipq8074 342 then: 343 properties: 344 clocks: 345 minItems: 5 346 maxItems: 5 347 clock-names: 348 items: 349 - const: iface # PCIe to SysNOC BIU clock 350 - const: axi_m # AXI Master clock 351 - const: axi_s # AXI Slave clock 352 - const: ahb # AHB clock 353 - const: aux # Auxiliary clock 354 resets: 355 minItems: 7 356 maxItems: 7 357 reset-names: 358 items: 359 - const: pipe # PIPE reset 360 - const: sleep # Sleep reset 361 - const: sticky # Core Sticky reset 362 - const: axi_m # AXI Master reset 363 - const: axi_s # AXI Slave reset 364 - const: ahb # AHB Reset 365 - const: axi_m_sticky # AXI Master Sticky reset 366 367 - if: 368 properties: 369 compatible: 370 contains: 371 enum: 372 - qcom,pcie-ipq6018 373 - qcom,pcie-ipq8074-gen3 374 then: 375 properties: 376 clocks: 377 minItems: 5 378 maxItems: 5 379 clock-names: 380 items: 381 - const: iface # PCIe to SysNOC BIU clock 382 - const: axi_m # AXI Master clock 383 - const: axi_s # AXI Slave clock 384 - const: axi_bridge # AXI bridge clock 385 - const: rchng 386 resets: 387 minItems: 8 388 maxItems: 8 389 reset-names: 390 items: 391 - const: pipe # PIPE reset 392 - const: sleep # Sleep reset 393 - const: sticky # Core Sticky reset 394 - const: axi_m # AXI Master reset 395 - const: axi_s # AXI Slave reset 396 - const: ahb # AHB Reset 397 - const: axi_m_sticky # AXI Master Sticky reset 398 - const: axi_s_sticky # AXI Slave Sticky reset 399 400 - if: 401 properties: 402 compatible: 403 contains: 404 enum: 405 - qcom,pcie-qcs404 406 then: 407 properties: 408 clocks: 409 minItems: 4 410 maxItems: 4 411 clock-names: 412 items: 413 - const: iface # AHB clock 414 - const: aux # Auxiliary clock 415 - const: master_bus # AXI Master clock 416 - const: slave_bus # AXI Slave clock 417 resets: 418 minItems: 6 419 maxItems: 6 420 reset-names: 421 items: 422 - const: axi_m # AXI Master reset 423 - const: axi_s # AXI Slave reset 424 - const: axi_m_sticky # AXI Master Sticky reset 425 - const: pipe_sticky # PIPE sticky reset 426 - const: pwr # PWR reset 427 - const: ahb # AHB reset 428 429 - if: 430 properties: 431 compatible: 432 contains: 433 enum: 434 - qcom,pcie-sdm845 435 then: 436 oneOf: 437 # Unfortunately the "optional" ref clock is used in the middle of the list 438 - properties: 439 clocks: 440 minItems: 8 441 maxItems: 8 442 clock-names: 443 items: 444 - const: pipe # PIPE clock 445 - const: aux # Auxiliary clock 446 - const: cfg # Configuration clock 447 - const: bus_master # Master AXI clock 448 - const: bus_slave # Slave AXI clock 449 - const: slave_q2a # Slave Q2A clock 450 - const: ref # REFERENCE clock 451 - const: tbu # PCIe TBU clock 452 - properties: 453 clocks: 454 minItems: 7 455 maxItems: 7 456 clock-names: 457 items: 458 - const: pipe # PIPE clock 459 - const: aux # Auxiliary clock 460 - const: cfg # Configuration clock 461 - const: bus_master # Master AXI clock 462 - const: bus_slave # Slave AXI clock 463 - const: slave_q2a # Slave Q2A clock 464 - const: tbu # PCIe TBU clock 465 properties: 466 resets: 467 maxItems: 1 468 reset-names: 469 items: 470 - const: pci # PCIe core reset 471 472 - if: 473 properties: 474 compatible: 475 contains: 476 enum: 477 - qcom,pcie-sdx55 478 then: 479 properties: 480 clocks: 481 minItems: 7 482 maxItems: 7 483 clock-names: 484 items: 485 - const: pipe # PIPE clock 486 - const: aux # Auxiliary clock 487 - const: cfg # Configuration clock 488 - const: bus_master # Master AXI clock 489 - const: bus_slave # Slave AXI clock 490 - const: slave_q2a # Slave Q2A clock 491 - const: sleep # PCIe Sleep clock 492 resets: 493 maxItems: 1 494 reset-names: 495 items: 496 - const: pci # PCIe core reset 497 498 - if: 499 not: 500 properties: 501 compatible: 502 contains: 503 enum: 504 - qcom,pcie-apq8064 505 - qcom,pcie-ipq4019 506 - qcom,pcie-ipq8064 507 - qcom,pcie-ipq8064v2 508 - qcom,pcie-ipq8074 509 - qcom,pcie-ipq8074-gen3 510 - qcom,pcie-qcs404 511 then: 512 required: 513 - power-domains 514 515 - if: 516 not: 517 properties: 518 compatible: 519 contains: 520 enum: 521 - qcom,pcie-msm8996 522 then: 523 required: 524 - resets 525 - reset-names 526 527 - if: 528 properties: 529 compatible: 530 contains: 531 enum: 532 - qcom,pcie-msm8996 533 - qcom,pcie-sdm845 534 then: 535 oneOf: 536 - properties: 537 interrupts: 538 maxItems: 1 539 interrupt-names: 540 items: 541 - const: msi 542 - properties: 543 interrupts: 544 minItems: 8 545 interrupt-names: 546 items: 547 - const: msi0 548 - const: msi1 549 - const: msi2 550 - const: msi3 551 - const: msi4 552 - const: msi5 553 - const: msi6 554 - const: msi7 555 556 - if: 557 properties: 558 compatible: 559 contains: 560 enum: 561 - qcom,pcie-apq8064 562 - qcom,pcie-apq8084 563 - qcom,pcie-ipq4019 564 - qcom,pcie-ipq6018 565 - qcom,pcie-ipq8064 566 - qcom,pcie-ipq8064-v2 567 - qcom,pcie-ipq8074 568 - qcom,pcie-ipq8074-gen3 569 - qcom,pcie-qcs404 570 then: 571 properties: 572 interrupts: 573 maxItems: 1 574 interrupt-names: 575 items: 576 - const: msi 577 578unevaluatedProperties: false 579 580examples: 581 - | 582 #include <dt-bindings/interrupt-controller/arm-gic.h> 583 pcie@1b500000 { 584 compatible = "qcom,pcie-ipq8064"; 585 reg = <0x1b500000 0x1000>, 586 <0x1b502000 0x80>, 587 <0x1b600000 0x100>, 588 <0x0ff00000 0x100000>; 589 reg-names = "dbi", "elbi", "parf", "config"; 590 device_type = "pci"; 591 linux,pci-domain = <0>; 592 bus-range = <0x00 0xff>; 593 num-lanes = <1>; 594 #address-cells = <3>; 595 #size-cells = <2>; 596 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, 597 <0x82000000 0 0 0x08000000 0 0x07e00000>; 598 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-names = "msi"; 600 #interrupt-cells = <1>; 601 interrupt-map-mask = <0 0 0 0x7>; 602 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, 603 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, 604 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, 605 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&gcc 41>, 607 <&gcc 43>, 608 <&gcc 44>, 609 <&gcc 42>, 610 <&gcc 248>; 611 clock-names = "core", "iface", "phy", "aux", "ref"; 612 resets = <&gcc 27>, 613 <&gcc 26>, 614 <&gcc 25>, 615 <&gcc 24>, 616 <&gcc 23>, 617 <&gcc 22>; 618 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 619 pinctrl-0 = <&pcie_pins_default>; 620 pinctrl-names = "default"; 621 vdda-supply = <&pm8921_s3>; 622 vdda_phy-supply = <&pm8921_lvs6>; 623 vdda_refclk-supply = <&ext_3p3v>; 624 }; 625 - | 626 #include <dt-bindings/interrupt-controller/arm-gic.h> 627 #include <dt-bindings/gpio/gpio.h> 628 pcie@fc520000 { 629 compatible = "qcom,pcie-apq8084"; 630 reg = <0xfc520000 0x2000>, 631 <0xff000000 0x1000>, 632 <0xff001000 0x1000>, 633 <0xff002000 0x2000>; 634 reg-names = "parf", "dbi", "elbi", "config"; 635 device_type = "pci"; 636 linux,pci-domain = <0>; 637 bus-range = <0x00 0xff>; 638 num-lanes = <1>; 639 #address-cells = <3>; 640 #size-cells = <2>; 641 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>, 642 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; 643 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-names = "msi"; 645 #interrupt-cells = <1>; 646 interrupt-map-mask = <0 0 0 0x7>; 647 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, 648 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, 649 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, 650 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&gcc 324>, 652 <&gcc 325>, 653 <&gcc 327>, 654 <&gcc 323>; 655 clock-names = "iface", "master_bus", "slave_bus", "aux"; 656 resets = <&gcc 81>; 657 reset-names = "core"; 658 power-domains = <&gcc 1>; 659 vdda-supply = <&pma8084_l3>; 660 phys = <&pciephy0>; 661 phy-names = "pciephy"; 662 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; 663 pinctrl-0 = <&pcie0_pins_default>; 664 pinctrl-names = "default"; 665 }; 666... 667