1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8550 PCI Express Root Complex 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 12 13description: 14 Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on 15 the Synopsys DesignWare PCIe IP. 16 17properties: 18 compatible: 19 oneOf: 20 - const: qcom,pcie-sm8550 21 - items: 22 - enum: 23 - qcom,sar2130p-pcie 24 - qcom,pcie-sm8650 25 - qcom,pcie-sm8750 26 - const: qcom,pcie-sm8550 27 28 reg: 29 minItems: 5 30 maxItems: 6 31 32 reg-names: 33 minItems: 5 34 items: 35 - const: parf # Qualcomm specific registers 36 - const: dbi # DesignWare PCIe registers 37 - const: elbi # External local bus interface registers 38 - const: atu # ATU address space 39 - const: config # PCIe configuration space 40 - const: mhi # MHI registers 41 42 clocks: 43 minItems: 7 44 maxItems: 9 45 46 clock-names: 47 minItems: 7 48 items: 49 - const: aux # Auxiliary clock 50 - const: cfg # Configuration clock 51 - const: bus_master # Master AXI clock 52 - const: bus_slave # Slave AXI clock 53 - const: slave_q2a # Slave Q2A clock 54 - const: ddrss_sf_tbu # PCIe SF TBU clock 55 - const: noc_aggr # Aggre NoC PCIe AXI clock 56 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock 57 - const: qmip_pcie_ahb # QMIP PCIe AHB clock 58 59 interrupts: 60 minItems: 8 61 maxItems: 9 62 63 interrupt-names: 64 minItems: 8 65 items: 66 - const: msi0 67 - const: msi1 68 - const: msi2 69 - const: msi3 70 - const: msi4 71 - const: msi5 72 - const: msi6 73 - const: msi7 74 - const: global 75 76 resets: 77 minItems: 1 78 maxItems: 2 79 80 reset-names: 81 minItems: 1 82 items: 83 - const: pci # PCIe core reset 84 - const: link_down # PCIe link down reset 85 86allOf: 87 - $ref: qcom,pcie-common.yaml# 88 89unevaluatedProperties: false 90 91examples: 92 - | 93 #include <dt-bindings/clock/qcom,sm8550-gcc.h> 94 #include <dt-bindings/gpio/gpio.h> 95 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 96 #include <dt-bindings/interrupt-controller/arm-gic.h> 97 98 soc { 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 pcie@1c00000 { 103 compatible = "qcom,pcie-sm8550"; 104 reg = <0 0x01c00000 0 0x3000>, 105 <0 0x60000000 0 0xf1d>, 106 <0 0x60000f20 0 0xa8>, 107 <0 0x60001000 0 0x1000>, 108 <0 0x60100000 0 0x100000>; 109 reg-names = "parf", "dbi", "elbi", "atu", "config"; 110 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 111 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 112 113 bus-range = <0x00 0xff>; 114 device_type = "pci"; 115 linux,pci-domain = <0>; 116 num-lanes = <2>; 117 118 #address-cells = <3>; 119 #size-cells = <2>; 120 121 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 122 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 123 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 124 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 125 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 126 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 127 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 128 clock-names = "aux", 129 "cfg", 130 "bus_master", 131 "bus_slave", 132 "slave_q2a", 133 "ddrss_sf_tbu", 134 "noc_aggr"; 135 136 dma-coherent; 137 138 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "msi0", "msi1", "msi2", "msi3", 148 "msi4", "msi5", "msi6", "msi7", "global"; 149 #interrupt-cells = <1>; 150 interrupt-map-mask = <0 0 0 0x7>; 151 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 152 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 153 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 154 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 155 156 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 157 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 158 interconnect-names = "pcie-mem", "cpu-pcie"; 159 160 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 161 <0x100 &apps_smmu 0x1401 0x1>; 162 163 phys = <&pcie0_phy>; 164 phy-names = "pciephy"; 165 166 pinctrl-0 = <&pcie0_default_state>; 167 pinctrl-names = "default"; 168 169 power-domains = <&gcc PCIE_0_GDSC>; 170 171 resets = <&gcc GCC_PCIE_0_BCR>; 172 reset-names = "pci"; 173 174 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 175 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 176 }; 177 }; 178