xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8550 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description:
14  Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
15  the Synopsys DesignWare PCIe IP.
16
17properties:
18  compatible:
19    oneOf:
20      - const: qcom,pcie-sm8550
21      - items:
22          - enum:
23              - qcom,sar2130p-pcie
24              - qcom,pcie-sm8650
25          - const: qcom,pcie-sm8550
26
27  reg:
28    minItems: 5
29    maxItems: 6
30
31  reg-names:
32    minItems: 5
33    items:
34      - const: parf # Qualcomm specific registers
35      - const: dbi # DesignWare PCIe registers
36      - const: elbi # External local bus interface registers
37      - const: atu # ATU address space
38      - const: config # PCIe configuration space
39      - const: mhi # MHI registers
40
41  clocks:
42    minItems: 7
43    maxItems: 9
44
45  clock-names:
46    minItems: 7
47    items:
48      - const: aux # Auxiliary clock
49      - const: cfg # Configuration clock
50      - const: bus_master # Master AXI clock
51      - const: bus_slave # Slave AXI clock
52      - const: slave_q2a # Slave Q2A clock
53      - const: ddrss_sf_tbu # PCIe SF TBU clock
54      - const: noc_aggr # Aggre NoC PCIe AXI clock
55      - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
56      - const: qmip_pcie_ahb # QMIP PCIe AHB clock
57
58  interrupts:
59    minItems: 8
60    maxItems: 8
61
62  interrupt-names:
63    items:
64      - const: msi0
65      - const: msi1
66      - const: msi2
67      - const: msi3
68      - const: msi4
69      - const: msi5
70      - const: msi6
71      - const: msi7
72
73  resets:
74    minItems: 1
75    maxItems: 2
76
77  reset-names:
78    minItems: 1
79    items:
80      - const: pci # PCIe core reset
81      - const: link_down # PCIe link down reset
82
83allOf:
84  - $ref: qcom,pcie-common.yaml#
85
86unevaluatedProperties: false
87
88examples:
89  - |
90    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
91    #include <dt-bindings/gpio/gpio.h>
92    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
93    #include <dt-bindings/interrupt-controller/arm-gic.h>
94
95    soc {
96        #address-cells = <2>;
97        #size-cells = <2>;
98
99        pcie@1c00000 {
100            compatible = "qcom,pcie-sm8550";
101            reg = <0 0x01c00000 0 0x3000>,
102                  <0 0x60000000 0 0xf1d>,
103                  <0 0x60000f20 0 0xa8>,
104                  <0 0x60001000 0 0x1000>,
105                  <0 0x60100000 0 0x100000>;
106            reg-names = "parf", "dbi", "elbi", "atu", "config";
107            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
108                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
109
110            bus-range = <0x00 0xff>;
111            device_type = "pci";
112            linux,pci-domain = <0>;
113            num-lanes = <2>;
114
115            #address-cells = <3>;
116            #size-cells = <2>;
117
118            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
119                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
120                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
121                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
122                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
123                     <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
124                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
125            clock-names = "aux",
126                          "cfg",
127                          "bus_master",
128                          "bus_slave",
129                          "slave_q2a",
130                          "ddrss_sf_tbu",
131                          "noc_aggr";
132
133            dma-coherent;
134
135            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
136                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
137                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
138                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
139                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
140                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
141                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
142                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
143            interrupt-names = "msi0", "msi1", "msi2", "msi3",
144                              "msi4", "msi5", "msi6", "msi7";
145            #interrupt-cells = <1>;
146            interrupt-map-mask = <0 0 0 0x7>;
147            interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
148                            <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
149                            <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
150                            <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
151
152            interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
153                            <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
154            interconnect-names = "pcie-mem", "cpu-pcie";
155
156            iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
157                        <0x100 &apps_smmu 0x1401 0x1>;
158
159            phys = <&pcie0_phy>;
160            phy-names = "pciephy";
161
162            pinctrl-0 = <&pcie0_default_state>;
163            pinctrl-names = "default";
164
165            power-domains = <&gcc PCIE_0_GDSC>;
166
167            resets = <&gcc GCC_PCIE_0_BCR>;
168            reset-names = "pci";
169
170            perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
171            wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
172        };
173    };
174