xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml (revision 7255fcc80d4b525cc10cfaaf7f485830d4ed2000) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8550 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description:
14  Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
15  the Synopsys DesignWare PCIe IP.
16
17properties:
18  compatible:
19    oneOf:
20      - const: qcom,pcie-sm8550
21      - items:
22          - enum:
23              - qcom,pcie-sm8650
24          - const: qcom,pcie-sm8550
25
26  reg:
27    minItems: 5
28    maxItems: 6
29
30  reg-names:
31    minItems: 5
32    items:
33      - const: parf # Qualcomm specific registers
34      - const: dbi # DesignWare PCIe registers
35      - const: elbi # External local bus interface registers
36      - const: atu # ATU address space
37      - const: config # PCIe configuration space
38      - const: mhi # MHI registers
39
40  clocks:
41    minItems: 7
42    maxItems: 8
43
44  clock-names:
45    minItems: 7
46    items:
47      - const: aux # Auxiliary clock
48      - const: cfg # Configuration clock
49      - const: bus_master # Master AXI clock
50      - const: bus_slave # Slave AXI clock
51      - const: slave_q2a # Slave Q2A clock
52      - const: ddrss_sf_tbu # PCIe SF TBU clock
53      - const: noc_aggr # Aggre NoC PCIe AXI clock
54      - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
55
56  interrupts:
57    minItems: 8
58    maxItems: 8
59
60  interrupt-names:
61    items:
62      - const: msi0
63      - const: msi1
64      - const: msi2
65      - const: msi3
66      - const: msi4
67      - const: msi5
68      - const: msi6
69      - const: msi7
70
71  resets:
72    minItems: 1
73    maxItems: 2
74
75  reset-names:
76    minItems: 1
77    items:
78      - const: pci # PCIe core reset
79      - const: link_down # PCIe link down reset
80
81allOf:
82  - $ref: qcom,pcie-common.yaml#
83
84unevaluatedProperties: false
85
86examples:
87  - |
88    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
89    #include <dt-bindings/gpio/gpio.h>
90    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
91    #include <dt-bindings/interrupt-controller/arm-gic.h>
92
93    soc {
94        #address-cells = <2>;
95        #size-cells = <2>;
96
97        pcie@1c00000 {
98            compatible = "qcom,pcie-sm8550";
99            reg = <0 0x01c00000 0 0x3000>,
100                  <0 0x60000000 0 0xf1d>,
101                  <0 0x60000f20 0 0xa8>,
102                  <0 0x60001000 0 0x1000>,
103                  <0 0x60100000 0 0x100000>;
104            reg-names = "parf", "dbi", "elbi", "atu", "config";
105            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
106                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
107
108            bus-range = <0x00 0xff>;
109            device_type = "pci";
110            linux,pci-domain = <0>;
111            num-lanes = <2>;
112
113            #address-cells = <3>;
114            #size-cells = <2>;
115
116            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
117                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
118                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
119                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
120                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
121                     <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
122                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
123            clock-names = "aux",
124                          "cfg",
125                          "bus_master",
126                          "bus_slave",
127                          "slave_q2a",
128                          "ddrss_sf_tbu",
129                          "noc_aggr";
130
131            dma-coherent;
132
133            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
134                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
135                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
136                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
137                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
138                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
139                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
140                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
141            interrupt-names = "msi0", "msi1", "msi2", "msi3",
142                              "msi4", "msi5", "msi6", "msi7";
143            #interrupt-cells = <1>;
144            interrupt-map-mask = <0 0 0 0x7>;
145            interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
146                            <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
147                            <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
148                            <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
149
150            interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
151                            <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
152            interconnect-names = "pcie-mem", "cpu-pcie";
153
154            iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
155                        <0x100 &apps_smmu 0x1401 0x1>;
156
157            phys = <&pcie0_phy>;
158            phy-names = "pciephy";
159
160            pinctrl-0 = <&pcie0_default_state>;
161            pinctrl-names = "default";
162
163            power-domains = <&gcc PCIE_0_GDSC>;
164
165            resets = <&gcc GCC_PCIE_0_BCR>;
166            reset-names = "pci";
167
168            perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
169            wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
170        };
171    };
172