1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8450 PCI Express Root Complex 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 12 13description: 14 Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys 15 DesignWare PCIe IP. 16 17properties: 18 compatible: 19 enum: 20 - qcom,pcie-sm8450-pcie0 21 - qcom,pcie-sm8450-pcie1 22 23 reg: 24 minItems: 5 25 maxItems: 6 26 27 reg-names: 28 minItems: 5 29 items: 30 - const: parf # Qualcomm specific registers 31 - const: dbi # DesignWare PCIe registers 32 - const: elbi # External local bus interface registers 33 - const: atu # ATU address space 34 - const: config # PCIe configuration space 35 - const: mhi # MHI registers 36 37 clocks: 38 minItems: 11 39 maxItems: 12 40 41 clock-names: 42 minItems: 11 43 items: 44 - const: pipe # PIPE clock 45 - const: pipe_mux # PIPE MUX 46 - const: phy_pipe # PIPE output clock 47 - const: ref # REFERENCE clock 48 - const: aux # Auxiliary clock 49 - const: cfg # Configuration clock 50 - const: bus_master # Master AXI clock 51 - const: bus_slave # Slave AXI clock 52 - const: slave_q2a # Slave Q2A clock 53 - const: ddrss_sf_tbu # PCIe SF TBU clock 54 - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock 55 - const: aggre1 # Aggre NoC PCIe1 AXI clock 56 57 interrupts: 58 minItems: 8 59 maxItems: 8 60 61 interrupt-names: 62 items: 63 - const: msi0 64 - const: msi1 65 - const: msi2 66 - const: msi3 67 - const: msi4 68 - const: msi5 69 - const: msi6 70 - const: msi7 71 72 resets: 73 maxItems: 1 74 75 reset-names: 76 items: 77 - const: pci 78 79allOf: 80 - $ref: qcom,pcie-common.yaml# 81 82unevaluatedProperties: false 83 84examples: 85 - | 86 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 87 #include <dt-bindings/clock/qcom,rpmh.h> 88 #include <dt-bindings/gpio/gpio.h> 89 #include <dt-bindings/interconnect/qcom,sm8450.h> 90 #include <dt-bindings/interrupt-controller/arm-gic.h> 91 92 soc { 93 #address-cells = <2>; 94 #size-cells = <2>; 95 96 pcie@1c00000 { 97 compatible = "qcom,pcie-sm8450-pcie0"; 98 reg = <0 0x01c00000 0 0x3000>, 99 <0 0x60000000 0 0xf1d>, 100 <0 0x60000f20 0 0xa8>, 101 <0 0x60001000 0 0x1000>, 102 <0 0x60100000 0 0x100000>; 103 reg-names = "parf", "dbi", "elbi", "atu", "config"; 104 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 105 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 106 107 bus-range = <0x00 0xff>; 108 device_type = "pci"; 109 linux,pci-domain = <0>; 110 max-link-speed = <2>; 111 num-lanes = <1>; 112 113 #address-cells = <3>; 114 #size-cells = <2>; 115 116 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 117 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 118 <&pcie0_phy>, 119 <&rpmhcc RPMH_CXO_CLK>, 120 <&gcc GCC_PCIE_0_AUX_CLK>, 121 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 122 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 123 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 124 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 125 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 126 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 127 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 128 clock-names = "pipe", 129 "pipe_mux", 130 "phy_pipe", 131 "ref", 132 "aux", 133 "cfg", 134 "bus_master", 135 "bus_slave", 136 "slave_q2a", 137 "ddrss_sf_tbu", 138 "aggre0", 139 "aggre1"; 140 141 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 149 interrupt-names = "msi0", "msi1", "msi2", "msi3", 150 "msi4", "msi5", "msi6", "msi7"; 151 #interrupt-cells = <1>; 152 interrupt-map-mask = <0 0 0 0x7>; 153 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 154 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 155 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 156 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 157 msi-map = <0x0 &gic_its 0x5981 0x1>, 158 <0x100 &gic_its 0x5980 0x1>; 159 msi-map-mask = <0xff00>; 160 161 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 162 <0x100 &apps_smmu 0x1c01 0x1>; 163 164 phys = <&pcie0_phy>; 165 phy-names = "pciephy"; 166 167 pinctrl-0 = <&pcie0_default_state>; 168 pinctrl-names = "default"; 169 170 power-domains = <&gcc PCIE_0_GDSC>; 171 172 resets = <&gcc GCC_PCIE_0_BCR>; 173 reset-names = "pci"; 174 175 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 176 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 177 }; 178 }; 179