xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml (revision beaea9c4ba2d8ef1b10223dc3a75a7d7be3e5cd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8150 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description:
14  Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
15  DesignWare PCIe IP.
16
17properties:
18  compatible:
19    oneOf:
20      - const: qcom,pcie-sm8150
21      - items:
22          - enum:
23              - qcom,pcie-qcs615
24          - const: qcom,pcie-sm8150
25
26  reg:
27    minItems: 5
28    maxItems: 6
29
30  reg-names:
31    minItems: 5
32    items:
33      - const: parf # Qualcomm specific registers
34      - const: dbi # DesignWare PCIe registers
35      - const: elbi # External local bus interface registers
36      - const: atu # ATU address space
37      - const: config # PCIe configuration space
38      - const: mhi # MHI registers
39
40  clocks:
41    minItems: 6
42    maxItems: 6
43
44  clock-names:
45    items:
46      - const: pipe # PIPE clock
47      - const: aux # Auxiliary clock
48      - const: cfg # Configuration clock
49      - const: bus_master # Master AXI clock
50      - const: bus_slave # Slave AXI clock
51      - const: slave_q2a # Slave Q2A clock
52
53  interrupts:
54    minItems: 8
55    maxItems: 9
56
57  interrupt-names:
58    minItems: 8
59    items:
60      - const: msi0
61      - const: msi1
62      - const: msi2
63      - const: msi3
64      - const: msi4
65      - const: msi5
66      - const: msi6
67      - const: msi7
68      - const: global
69
70  resets:
71    maxItems: 1
72
73  reset-names:
74    items:
75      - const: pci
76
77allOf:
78  - $ref: qcom,pcie-common.yaml#
79
80unevaluatedProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
85    #include <dt-bindings/clock/qcom,rpmh.h>
86    #include <dt-bindings/gpio/gpio.h>
87    #include <dt-bindings/interconnect/qcom,sm8150.h>
88    #include <dt-bindings/interrupt-controller/arm-gic.h>
89
90    soc {
91        #address-cells = <2>;
92        #size-cells = <2>;
93        pcie@1c00000 {
94            compatible = "qcom,pcie-sm8150";
95            reg = <0 0x01c00000 0 0x3000>,
96                  <0 0x60000000 0 0xf1d>,
97                  <0 0x60000f20 0 0xa8>,
98                  <0 0x60001000 0 0x1000>,
99                  <0 0x60100000 0 0x100000>;
100            reg-names = "parf", "dbi", "elbi", "atu", "config";
101            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
102                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
103
104            bus-range = <0x00 0xff>;
105            device_type = "pci";
106            linux,pci-domain = <0>;
107            num-lanes = <1>;
108
109            #address-cells = <3>;
110            #size-cells = <2>;
111
112            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
113                     <&gcc GCC_PCIE_0_AUX_CLK>,
114                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
115                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
116                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
117                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
118            clock-names = "pipe",
119                          "aux",
120                          "cfg",
121                          "bus_master",
122                          "bus_slave",
123                          "slave_q2a";
124
125            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
126                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
127                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
128                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
129                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
130                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
131                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
132                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
133                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
134            interrupt-names = "msi0", "msi1", "msi2", "msi3",
135                              "msi4", "msi5", "msi6", "msi7", "global";
136            #interrupt-cells = <1>;
137            interrupt-map-mask = <0 0 0 0x7>;
138            interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
139                            <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
140                            <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
141                            <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
142
143            iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
144                        <0x100 &apps_smmu 0x1d81 0x1>;
145
146            phys = <&pcie0_phy>;
147            phy-names = "pciephy";
148
149            pinctrl-0 = <&pcie0_default_state>;
150            pinctrl-names = "default";
151
152            power-domains = <&gcc PCIE_0_GDSC>;
153
154            resets = <&gcc GCC_PCIE_0_BCR>;
155            reset-names = "pci";
156
157            perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
158            wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
159        };
160    };
161