xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml (revision fa79e55d467366a2c52c68a261a0d6ea5f8a6534) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC8180x PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description:
14  Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
15  DesignWare PCIe IP.
16
17properties:
18  compatible:
19    const: qcom,pcie-sc8180x
20
21  reg:
22    minItems: 5
23    maxItems: 6
24
25  reg-names:
26    minItems: 5
27    items:
28      - const: parf # Qualcomm specific registers
29      - const: dbi # DesignWare PCIe registers
30      - const: elbi # External local bus interface registers
31      - const: atu # ATU address space
32      - const: config # PCIe configuration space
33      - const: mhi # MHI registers
34
35  clocks:
36    minItems: 8
37    maxItems: 8
38
39  clock-names:
40    items:
41      - const: pipe # PIPE clock
42      - const: aux # Auxiliary clock
43      - const: cfg # Configuration clock
44      - const: bus_master # Master AXI clock
45      - const: bus_slave # Slave AXI clock
46      - const: slave_q2a # Slave Q2A clock
47      - const: ref # REFERENCE clock
48      - const: tbu # PCIe TBU clock
49
50  interrupts:
51    minItems: 8
52    maxItems: 9
53
54  interrupt-names:
55    minItems: 8
56    items:
57      - const: msi0
58      - const: msi1
59      - const: msi2
60      - const: msi3
61      - const: msi4
62      - const: msi5
63      - const: msi6
64      - const: msi7
65      - const: global
66
67  resets:
68    maxItems: 1
69
70  reset-names:
71    items:
72      - const: pci
73
74allOf:
75  - $ref: qcom,pcie-common.yaml#
76
77unevaluatedProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
82    #include <dt-bindings/interconnect/qcom,sc8180x.h>
83    #include <dt-bindings/interrupt-controller/arm-gic.h>
84
85    soc {
86        #address-cells = <2>;
87        #size-cells = <2>;
88
89        pcie@1c00000 {
90            compatible = "qcom,pcie-sc8180x";
91            reg = <0 0x01c00000 0 0x3000>,
92                  <0 0x60000000 0 0xf1d>,
93                  <0 0x60000f20 0 0xa8>,
94                  <0 0x60001000 0 0x1000>,
95                  <0 0x60100000 0 0x100000>;
96            reg-names = "parf",
97                        "dbi",
98                        "elbi",
99                        "atu",
100                        "config";
101            ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
102                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
103
104            bus-range = <0x00 0xff>;
105            device_type = "pci";
106            linux,pci-domain = <0>;
107            num-lanes = <2>;
108
109            #address-cells = <3>;
110            #size-cells = <2>;
111
112            assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
113            assigned-clock-rates = <19200000>;
114
115            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
116                     <&gcc GCC_PCIE_0_AUX_CLK>,
117                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
118                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
119                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
120                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
121                     <&gcc GCC_PCIE_0_CLKREF_CLK>,
122                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
123            clock-names = "pipe",
124                          "aux",
125                          "cfg",
126                          "bus_master",
127                          "bus_slave",
128                          "slave_q2a",
129                          "ref",
130                          "tbu";
131
132            dma-coherent;
133
134            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
135                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
136                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
137                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
138                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
139                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
140                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
141                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
142                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
143            interrupt-names = "msi0",
144                          "msi1",
145                          "msi2",
146                          "msi3",
147                          "msi4",
148                          "msi5",
149                          "msi6",
150                          "msi7",
151                          "global";
152            #interrupt-cells = <1>;
153            interrupt-map-mask = <0 0 0 0x7>;
154            interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
155                            <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
156                            <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
157                            <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
158
159            interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
160                            <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
161            interconnect-names = "pcie-mem", "cpu-pcie";
162
163            iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
164                        <0x100 &apps_smmu 0x1d81 0x1>;
165
166            phys = <&pcie0_phy>;
167            phy-names = "pciephy";
168
169            power-domains = <&gcc PCIE_0_GDSC>;
170
171            resets = <&gcc GCC_PCIE_0_BCR>;
172            reset-names = "pci";
173        };
174    };
175