xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml (revision df9c299371054cb725eef730fd0f1d0fe2ed6bb0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SA8775p PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description:
14  Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
15  DesignWare PCIe IP.
16
17properties:
18  compatible:
19    const: qcom,pcie-sa8775p
20
21  reg:
22    minItems: 6
23    maxItems: 6
24
25  reg-names:
26    items:
27      - const: parf # Qualcomm specific registers
28      - const: dbi # DesignWare PCIe registers
29      - const: elbi # External local bus interface registers
30      - const: atu # ATU address space
31      - const: config # PCIe configuration space
32      - const: mhi # MHI registers
33
34  clocks:
35    minItems: 5
36    maxItems: 5
37
38  clock-names:
39    items:
40      - const: aux # Auxiliary clock
41      - const: cfg # Configuration clock
42      - const: bus_master # Master AXI clock
43      - const: bus_slave # Slave AXI clock
44      - const: slave_q2a # Slave Q2A clock
45
46  interrupts:
47    minItems: 8
48    maxItems: 9
49
50  interrupt-names:
51    minItems: 8
52    items:
53      - const: msi0
54      - const: msi1
55      - const: msi2
56      - const: msi3
57      - const: msi4
58      - const: msi5
59      - const: msi6
60      - const: msi7
61      - const: global
62
63  resets:
64    maxItems: 1
65
66  reset-names:
67    items:
68      - const: pci
69
70required:
71  - interconnects
72  - interconnect-names
73
74allOf:
75  - $ref: qcom,pcie-common.yaml#
76
77unevaluatedProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
82    #include <dt-bindings/clock/qcom,rpmh.h>
83    #include <dt-bindings/gpio/gpio.h>
84    #include <dt-bindings/interrupt-controller/arm-gic.h>
85    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
86
87    soc {
88        #address-cells = <2>;
89        #size-cells = <2>;
90
91        pcie@1c00000 {
92            compatible = "qcom,pcie-sa8775p";
93            reg = <0x0 0x01c00000 0x0 0x3000>,
94                  <0x0 0x40000000 0x0 0xf20>,
95                  <0x0 0x40000f20 0x0 0xa8>,
96                  <0x0 0x40001000 0x0 0x4000>,
97                  <0x0 0x40100000 0x0 0x100000>,
98                  <0x0 0x01c03000 0x0 0x1000>;
99            reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
100            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
101                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
102
103            bus-range = <0x00 0xff>;
104            device_type = "pci";
105            linux,pci-domain = <0>;
106            num-lanes = <2>;
107
108            #address-cells = <3>;
109            #size-cells = <2>;
110
111            assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
112            assigned-clock-rates = <19200000>;
113
114            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
115                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
116                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
117                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
118                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
119            clock-names = "aux",
120                          "cfg",
121                          "bus_master",
122                          "bus_slave",
123                          "slave_q2a";
124
125            dma-coherent;
126
127            interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
128                         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
129                         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
130                         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
131                         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
132                         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
133                         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
134                         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
135                         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
136            interrupt-names = "msi0",
137                              "msi1",
138                              "msi2",
139                              "msi3",
140                              "msi4",
141                              "msi5",
142                              "msi6",
143                              "msi7",
144                              "global";
145            #interrupt-cells = <1>;
146            interrupt-map-mask = <0 0 0 0x7>;
147            interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
148                            <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
149                            <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
150                            <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
151
152            interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
153                            <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
154            interconnect-names = "pcie-mem", "cpu-pcie";
155
156            iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
157                        <0x100 &pcie_smmu 0x0001 0x1>;
158
159            phys = <&pcie0_phy>;
160            phy-names = "pciephy";
161
162            power-domains = <&gcc PCIE_0_GDSC>;
163
164            resets = <&gcc GCC_PCIE_0_BCR>;
165            reset-names = "pci";
166
167            perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
168            wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
169        };
170    };
171