xref: /linux/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml (revision beaea9c4ba2d8ef1b10223dc3a75a7d7be3e5cd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SA8775p PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12
13description:
14  Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
15  DesignWare PCIe IP.
16
17properties:
18  compatible:
19    oneOf:
20      - const: qcom,pcie-sa8775p
21      - items:
22          - enum:
23              - qcom,pcie-qcs8300
24          - const: qcom,pcie-sa8775p
25
26  reg:
27    minItems: 6
28    maxItems: 6
29
30  reg-names:
31    items:
32      - const: parf # Qualcomm specific registers
33      - const: dbi # DesignWare PCIe registers
34      - const: elbi # External local bus interface registers
35      - const: atu # ATU address space
36      - const: config # PCIe configuration space
37      - const: mhi # MHI registers
38
39  clocks:
40    minItems: 5
41    maxItems: 5
42
43  clock-names:
44    items:
45      - const: aux # Auxiliary clock
46      - const: cfg # Configuration clock
47      - const: bus_master # Master AXI clock
48      - const: bus_slave # Slave AXI clock
49      - const: slave_q2a # Slave Q2A clock
50
51  interrupts:
52    minItems: 8
53    maxItems: 9
54
55  interrupt-names:
56    minItems: 8
57    items:
58      - const: msi0
59      - const: msi1
60      - const: msi2
61      - const: msi3
62      - const: msi4
63      - const: msi5
64      - const: msi6
65      - const: msi7
66      - const: global
67
68  resets:
69    items:
70      - description: PCIe controller reset
71      - description: PCIe link down reset
72
73  reset-names:
74    items:
75      - const: pci
76      - const: link_down
77
78required:
79  - interconnects
80  - interconnect-names
81
82allOf:
83  - $ref: qcom,pcie-common.yaml#
84
85unevaluatedProperties: false
86
87examples:
88  - |
89    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
90    #include <dt-bindings/clock/qcom,rpmh.h>
91    #include <dt-bindings/gpio/gpio.h>
92    #include <dt-bindings/interrupt-controller/arm-gic.h>
93    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
94
95    soc {
96        #address-cells = <2>;
97        #size-cells = <2>;
98
99        pcie@1c00000 {
100            compatible = "qcom,pcie-sa8775p";
101            reg = <0x0 0x01c00000 0x0 0x3000>,
102                  <0x0 0x40000000 0x0 0xf20>,
103                  <0x0 0x40000f20 0x0 0xa8>,
104                  <0x0 0x40001000 0x0 0x4000>,
105                  <0x0 0x40100000 0x0 0x100000>,
106                  <0x0 0x01c03000 0x0 0x1000>;
107            reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
108            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
109                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
110
111            bus-range = <0x00 0xff>;
112            device_type = "pci";
113            linux,pci-domain = <0>;
114            num-lanes = <2>;
115
116            #address-cells = <3>;
117            #size-cells = <2>;
118
119            assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
120            assigned-clock-rates = <19200000>;
121
122            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
123                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
124                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
125                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
126                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
127            clock-names = "aux",
128                          "cfg",
129                          "bus_master",
130                          "bus_slave",
131                          "slave_q2a";
132
133            dma-coherent;
134
135            interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
136                         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
137                         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
138                         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
139                         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
140                         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
141                         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
142                         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
143                         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
144            interrupt-names = "msi0",
145                              "msi1",
146                              "msi2",
147                              "msi3",
148                              "msi4",
149                              "msi5",
150                              "msi6",
151                              "msi7",
152                              "global";
153            #interrupt-cells = <1>;
154            interrupt-map-mask = <0 0 0 0x7>;
155            interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
156                            <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
157                            <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
158                            <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
159
160            interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
161                            <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
162            interconnect-names = "pcie-mem", "cpu-pcie";
163
164            iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
165                        <0x100 &pcie_smmu 0x0001 0x1>;
166
167            phys = <&pcie0_phy>;
168            phy-names = "pciephy";
169
170            power-domains = <&gcc PCIE_0_GDSC>;
171
172            resets = <&gcc GCC_PCIE_0_BCR>,
173                     <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
174            reset-names = "pci",
175                          "link_down";
176
177            perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
178            wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
179        };
180    };
181