1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm PCIe Endpoint Controller 8 9maintainers: 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11 12properties: 13 compatible: 14 oneOf: 15 - enum: 16 - qcom,sdx55-pcie-ep 17 - qcom,sm8450-pcie-ep 18 - items: 19 - const: qcom,sdx65-pcie-ep 20 - const: qcom,sdx55-pcie-ep 21 22 reg: 23 items: 24 - description: Qualcomm-specific PARF configuration registers 25 - description: DesignWare PCIe registers 26 - description: External local bus interface registers 27 - description: Address Translation Unit (ATU) registers 28 - description: Memory region used to map remote RC address space 29 - description: BAR memory region 30 31 reg-names: 32 items: 33 - const: parf 34 - const: dbi 35 - const: elbi 36 - const: atu 37 - const: addr_space 38 - const: mmio 39 40 clocks: 41 minItems: 7 42 maxItems: 8 43 44 clock-names: 45 minItems: 7 46 maxItems: 8 47 48 qcom,perst-regs: 49 description: Reference to a syscon representing TCSR followed by the two 50 offsets within syscon for Perst enable and Perst separation 51 enable registers 52 $ref: /schemas/types.yaml#/definitions/phandle-array 53 items: 54 - items: 55 - description: Syscon to TCSR system registers 56 - description: Perst enable offset 57 - description: Perst separation enable offset 58 59 interrupts: 60 items: 61 - description: PCIe Global interrupt 62 - description: PCIe Doorbell interrupt 63 64 interrupt-names: 65 items: 66 - const: global 67 - const: doorbell 68 69 reset-gpios: 70 description: GPIO used as PERST# input signal 71 maxItems: 1 72 73 wake-gpios: 74 description: GPIO used as WAKE# output signal 75 maxItems: 1 76 77 interconnects: 78 maxItems: 2 79 80 interconnect-names: 81 items: 82 - const: pcie-mem 83 - const: cpu-pcie 84 85 resets: 86 maxItems: 1 87 88 reset-names: 89 const: core 90 91 power-domains: 92 maxItems: 1 93 94 phys: 95 maxItems: 1 96 97 phy-names: 98 const: pciephy 99 100 num-lanes: 101 default: 2 102 103required: 104 - compatible 105 - reg 106 - reg-names 107 - clocks 108 - clock-names 109 - interrupts 110 - interrupt-names 111 - reset-gpios 112 - interconnects 113 - interconnect-names 114 - resets 115 - reset-names 116 - power-domains 117 118allOf: 119 - $ref: pci-ep.yaml# 120 - if: 121 properties: 122 compatible: 123 contains: 124 enum: 125 - qcom,sdx55-pcie-ep 126 then: 127 properties: 128 clocks: 129 items: 130 - description: PCIe Auxiliary clock 131 - description: PCIe CFG AHB clock 132 - description: PCIe Master AXI clock 133 - description: PCIe Slave AXI clock 134 - description: PCIe Slave Q2A AXI clock 135 - description: PCIe Sleep clock 136 - description: PCIe Reference clock 137 clock-names: 138 items: 139 - const: aux 140 - const: cfg 141 - const: bus_master 142 - const: bus_slave 143 - const: slave_q2a 144 - const: sleep 145 - const: ref 146 147 - if: 148 properties: 149 compatible: 150 contains: 151 enum: 152 - qcom,sm8450-pcie-ep 153 then: 154 properties: 155 clocks: 156 items: 157 - description: PCIe Auxiliary clock 158 - description: PCIe CFG AHB clock 159 - description: PCIe Master AXI clock 160 - description: PCIe Slave AXI clock 161 - description: PCIe Slave Q2A AXI clock 162 - description: PCIe Reference clock 163 - description: PCIe DDRSS SF TBU clock 164 - description: PCIe AGGRE NOC AXI clock 165 clock-names: 166 items: 167 - const: aux 168 - const: cfg 169 - const: bus_master 170 - const: bus_slave 171 - const: slave_q2a 172 - const: ref 173 - const: ddrss_sf_tbu 174 - const: aggre_noc_axi 175 176unevaluatedProperties: false 177 178examples: 179 - | 180 #include <dt-bindings/clock/qcom,gcc-sdx55.h> 181 #include <dt-bindings/gpio/gpio.h> 182 #include <dt-bindings/interconnect/qcom,sdx55.h> 183 #include <dt-bindings/interrupt-controller/arm-gic.h> 184 185 pcie_ep: pcie-ep@1c00000 { 186 compatible = "qcom,sdx55-pcie-ep"; 187 reg = <0x01c00000 0x3000>, 188 <0x40000000 0xf1d>, 189 <0x40000f20 0xc8>, 190 <0x40001000 0x1000>, 191 <0x40002000 0x1000>, 192 <0x01c03000 0x3000>; 193 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 194 "mmio"; 195 196 clocks = <&gcc GCC_PCIE_AUX_CLK>, 197 <&gcc GCC_PCIE_CFG_AHB_CLK>, 198 <&gcc GCC_PCIE_MSTR_AXI_CLK>, 199 <&gcc GCC_PCIE_SLV_AXI_CLK>, 200 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 201 <&gcc GCC_PCIE_SLEEP_CLK>, 202 <&gcc GCC_PCIE_0_CLKREF_CLK>; 203 clock-names = "aux", "cfg", "bus_master", "bus_slave", 204 "slave_q2a", "sleep", "ref"; 205 206 qcom,perst-regs = <&tcsr 0xb258 0xb270>; 207 208 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-names = "global", "doorbell"; 211 interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, 212 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; 213 interconnect-names = "pcie-mem", "cpu-pcie"; 214 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; 215 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; 216 resets = <&gcc GCC_PCIE_BCR>; 217 reset-names = "core"; 218 power-domains = <&gcc PCIE_GDSC>; 219 phys = <&pcie0_lane>; 220 phy-names = "pciephy"; 221 max-link-speed = <3>; 222 num-lanes = <2>; 223 }; 224