1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based) 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 13 14description: | 15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of 17 the controller instances are dual mode where in they can work either in 18 Root Port mode or Endpoint mode but one at a time. 19 20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device 21 tree bindings. 22 23properties: 24 compatible: 25 enum: 26 - nvidia,tegra194-pcie 27 28 reg: 29 items: 30 - description: controller's application logic registers 31 - description: configuration registers 32 - description: iATU and DMA registers. This is where the iATU (internal 33 Address Translation Unit) registers of the PCIe core are made 34 available for software access. 35 - description: aperture where the Root Port's own configuration 36 registers are available. 37 38 reg-names: 39 items: 40 - const: appl 41 - const: config 42 - const: atu_dma 43 - const: dbi 44 45 interrupts: 46 items: 47 - description: controller interrupt 48 - description: MSI interrupt 49 50 interrupt-names: 51 items: 52 - const: intr 53 - const: msi 54 55 clocks: 56 items: 57 - description: module clock 58 59 clock-names: 60 items: 61 - const: core 62 63 resets: 64 items: 65 - description: APB bus interface reset 66 - description: module reset 67 68 reset-names: 69 items: 70 - const: apb 71 - const: core 72 73 phys: 74 minItems: 1 75 maxItems: 8 76 77 phy-names: 78 minItems: 1 79 items: 80 - const: p2u-0 81 - const: p2u-1 82 - const: p2u-2 83 - const: p2u-3 84 - const: p2u-4 85 - const: p2u-5 86 - const: p2u-6 87 - const: p2u-7 88 89 power-domains: 90 maxItems: 1 91 description: | 92 A phandle to the node that controls power to the respective PCIe 93 controller and a specifier name for the PCIe controller. 94 95 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file. 96 97 interconnects: 98 items: 99 - description: memory read client 100 - description: memory write client 101 102 interconnect-names: 103 items: 104 - const: dma-mem # read 105 - const: write 106 107 dma-coherent: true 108 109 nvidia,bpmp: 110 $ref: /schemas/types.yaml#/definitions/phandle-array 111 description: | 112 Must contain a pair of phandles to BPMP controller node followed by 113 controller ID. Following are the controller IDs for each controller: 114 115 0: C0 116 1: C1 117 2: C2 118 3: C3 119 4: C4 120 5: C5 121 items: 122 - items: 123 - description: phandle to BPMP controller node 124 - description: PCIe controller ID 125 maximum: 5 126 127 nvidia,update-fc-fixup: 128 description: | 129 This is a boolean property and needs to be present to improve performance 130 when a platform is designed in such a way that it satisfies at least one 131 of the following conditions thereby enabling Root Port to exchange 132 optimum number of FC (Flow Control) credits with downstream devices: 133 134 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 135 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and 136 a) speed is Gen-2 and MPS is 256B 137 b) speed is >= Gen-3 with any MPS 138 139 $ref: /schemas/types.yaml#/definitions/flag 140 141 nvidia,aspm-cmrt-us: 142 description: Common Mode Restore Time for proper operation of ASPM to be 143 specified in microseconds 144 145 nvidia,aspm-pwr-on-t-us: 146 description: Power On time for proper operation of ASPM to be specified in 147 microseconds 148 149 nvidia,aspm-l0s-entrance-latency-us: 150 description: ASPM L0s entrance latency to be specified in microseconds 151 152 vddio-pex-ctl-supply: 153 description: A phandle to the regulator supply for PCIe side band signals. 154 155 vpcie3v3-supply: 156 description: A phandle to the regulator node that supplies 3.3V to the slot 157 if the platform has one such slot, e.g., x16 slot owned by C5 controller 158 in p2972-0000 platform. 159 160 vpcie12v-supply: 161 description: A phandle to the regulator node that supplies 12V to the slot 162 if the platform has one such slot, e.g., x16 slot owned by C5 controller 163 in p2972-0000 platform. 164 165allOf: 166 - $ref: /schemas/pci/snps,dw-pcie.yaml# 167 168unevaluatedProperties: false 169 170required: 171 - interrupts 172 - interrupt-names 173 - interrupt-map 174 - interrupt-map-mask 175 - clocks 176 - clock-names 177 - resets 178 - reset-names 179 - power-domains 180 - vddio-pex-ctl-supply 181 - num-lanes 182 - phys 183 - phy-names 184 - nvidia,bpmp 185 186examples: 187 - | 188 #include <dt-bindings/clock/tegra194-clock.h> 189 #include <dt-bindings/interrupt-controller/arm-gic.h> 190 #include <dt-bindings/power/tegra194-powergate.h> 191 #include <dt-bindings/reset/tegra194-reset.h> 192 193 bus@0 { 194 #address-cells = <2>; 195 #size-cells = <2>; 196 ranges = <0x0 0x0 0x0 0x8 0x0>; 197 198 pcie@14180000 { 199 compatible = "nvidia,tegra194-pcie"; 200 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 201 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 202 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 203 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 204 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 205 reg-names = "appl", "config", "atu_dma", "dbi"; 206 207 #address-cells = <3>; 208 #size-cells = <2>; 209 device_type = "pci"; 210 num-lanes = <8>; 211 linux,pci-domain = <0>; 212 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 215 216 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 217 clock-names = "core"; 218 219 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 220 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 221 reset-names = "apb", "core"; 222 223 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 224 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 225 interrupt-names = "intr", "msi"; 226 227 #interrupt-cells = <1>; 228 interrupt-map-mask = <0 0 0 0>; 229 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 230 231 nvidia,bpmp = <&bpmp 0>; 232 233 supports-clkreq; 234 nvidia,aspm-cmrt-us = <60>; 235 nvidia,aspm-pwr-on-t-us = <20>; 236 nvidia,aspm-l0s-entrance-latency-us = <3>; 237 238 bus-range = <0x0 0xff>; 239 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */ 240 <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */ 241 <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */ 242 243 vddio-pex-ctl-supply = <&vdd_1v8ao>; 244 vpcie3v3-supply = <&vdd_3v3_pcie>; 245 vpcie12v-supply = <&vdd_12v_pcie>; 246 247 phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, 248 <&p2u_hsio_5>; 249 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 250 }; 251 }; 252