1* Marvell EBU PCIe interfaces 2 3Mandatory properties: 4 5- compatible: one of the following values: 6 marvell,armada-370-pcie 7 marvell,armada-xp-pcie 8 marvell,dove-pcie 9 marvell,kirkwood-pcie 10- #address-cells, set to <3> 11- #size-cells, set to <2> 12- #interrupt-cells, set to <1> 13- bus-range: PCI bus numbers covered 14- device_type, set to "pci" 15- ranges: ranges describing the MMIO registers to control the PCIe 16 interfaces, and ranges describing the MBus windows needed to access 17 the memory and I/O regions of each PCIe interface. 18- msi-parent: Link to the hardware entity that serves as the Message 19 Signaled Interrupt controller for this PCI controller. 20 21The ranges describing the MMIO registers have the following layout: 22 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s 24 25where: 26 27 * r is a 32-bits value that gives the offset of the MMIO 28 registers of this PCIe interface, from the base of the internal 29 registers. 30 31 * s is a 32-bits value that give the size of this MMIO 32 registers area. This range entry translates the '0x82000000 0 r' PCI 33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part 34 of the internal register window (as identified by MBUS_ID(0xf0, 35 0x01)). 36 37The ranges describing the MBus windows have the following layout: 38 39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 40 41where: 42 43 * t is the type of the MBus window (as defined by the standard PCI DT 44 bindings), 1 for I/O and 2 for memory. 45 46 * s is the PCI slot that corresponds to this PCIe interface 47 48 * w is the 'target ID' value for the MBus window 49 50 * a the 'attribute' value for the MBus window. 51 52Since the location and size of the different MBus windows is not fixed in 53hardware, and only determined in runtime, those ranges cover the full first 544 GB of the physical address space, and do not translate into a valid CPU 55address. 56 57In addition, the device tree node must have sub-nodes describing each 58PCIe interface, having the following mandatory properties: 59 60- reg: used only for interrupt mapping, so only the first four bytes 61 are used to refer to the correct bus number and device number. 62- assigned-addresses: reference to the MMIO registers used to control 63 this PCIe interface. 64- clocks: the clock associated to this PCIe interface 65- marvell,pcie-port: the physical PCIe port number 66- status: either "disabled" or "okay" 67- device_type, set to "pci" 68- #address-cells, set to <3> 69- #size-cells, set to <2> 70- #interrupt-cells, set to <1> 71- ranges, translating the MBus windows ranges of the parent node into 72 standard PCI addresses. 73- interrupt-map-mask and interrupt-map, standard PCI properties to 74 define the mapping of the PCIe interface to interrupt numbers. 75 76and the following optional properties: 77- marvell,pcie-lane: the physical PCIe lane number, for ports having 78 multiple lanes. If this property is not found, we assume that the 79 value is 0. 80- reset-gpios: optional gpio to PERST# 81- reset-delay-us: delay in us to wait after reset de-assertion, if not 82 specified will default to 100ms, as required by the PCIe specification. 83 84Example: 85 86pcie-controller { 87 compatible = "marvell,armada-xp-pcie"; 88 status = "disabled"; 89 device_type = "pci"; 90 91 #address-cells = <3>; 92 #size-cells = <2>; 93 94 bus-range = <0x00 0xff>; 95 msi-parent = <&mpic>; 96 97 ranges = 98 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 99 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 100 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 101 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 102 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 103 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 104 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 105 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 106 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 107 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 108 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 109 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 110 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 111 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 112 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 113 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 114 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 115 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 116 117 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 118 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 119 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 120 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 121 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 122 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 123 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 124 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 125 126 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 127 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ 128 129 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 130 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 131 132 pcie@1,0 { 133 device_type = "pci"; 134 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 135 reg = <0x0800 0 0 0 0>; 136 #address-cells = <3>; 137 #size-cells = <2>; 138 #interrupt-cells = <1>; 139 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 140 0x81000000 0 0 0x81000000 0x1 0 1 0>; 141 interrupt-map-mask = <0 0 0 0>; 142 interrupt-map = <0 0 0 0 &mpic 58>; 143 marvell,pcie-port = <0>; 144 marvell,pcie-lane = <0>; 145 /* low-active PERST# reset on GPIO 25 */ 146 reset-gpios = <&gpio0 25 1>; 147 /* wait 20ms for device settle after reset deassertion */ 148 reset-delay-us = <20000>; 149 clocks = <&gateclk 5>; 150 status = "disabled"; 151 }; 152 153 pcie@2,0 { 154 device_type = "pci"; 155 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 156 reg = <0x1000 0 0 0 0>; 157 #address-cells = <3>; 158 #size-cells = <2>; 159 #interrupt-cells = <1>; 160 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 161 0x81000000 0 0 0x81000000 0x2 0 1 0>; 162 interrupt-map-mask = <0 0 0 0>; 163 interrupt-map = <0 0 0 0 &mpic 59>; 164 marvell,pcie-port = <0>; 165 marvell,pcie-lane = <1>; 166 clocks = <&gateclk 6>; 167 status = "disabled"; 168 }; 169 170 pcie@3,0 { 171 device_type = "pci"; 172 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 173 reg = <0x1800 0 0 0 0>; 174 #address-cells = <3>; 175 #size-cells = <2>; 176 #interrupt-cells = <1>; 177 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 178 0x81000000 0 0 0x81000000 0x3 0 1 0>; 179 interrupt-map-mask = <0 0 0 0>; 180 interrupt-map = <0 0 0 0 &mpic 60>; 181 marvell,pcie-port = <0>; 182 marvell,pcie-lane = <2>; 183 clocks = <&gateclk 7>; 184 status = "disabled"; 185 }; 186 187 pcie@4,0 { 188 device_type = "pci"; 189 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 190 reg = <0x2000 0 0 0 0>; 191 #address-cells = <3>; 192 #size-cells = <2>; 193 #interrupt-cells = <1>; 194 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 195 0x81000000 0 0 0x81000000 0x4 0 1 0>; 196 interrupt-map-mask = <0 0 0 0>; 197 interrupt-map = <0 0 0 0 &mpic 61>; 198 marvell,pcie-port = <0>; 199 marvell,pcie-lane = <3>; 200 clocks = <&gateclk 8>; 201 status = "disabled"; 202 }; 203 204 pcie@5,0 { 205 device_type = "pci"; 206 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 207 reg = <0x2800 0 0 0 0>; 208 #address-cells = <3>; 209 #size-cells = <2>; 210 #interrupt-cells = <1>; 211 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 212 0x81000000 0 0 0x81000000 0x5 0 1 0>; 213 interrupt-map-mask = <0 0 0 0>; 214 interrupt-map = <0 0 0 0 &mpic 62>; 215 marvell,pcie-port = <1>; 216 marvell,pcie-lane = <0>; 217 clocks = <&gateclk 9>; 218 status = "disabled"; 219 }; 220 221 pcie@6,0 { 222 device_type = "pci"; 223 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 224 reg = <0x3000 0 0 0 0>; 225 #address-cells = <3>; 226 #size-cells = <2>; 227 #interrupt-cells = <1>; 228 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 229 0x81000000 0 0 0x81000000 0x6 0 1 0>; 230 interrupt-map-mask = <0 0 0 0>; 231 interrupt-map = <0 0 0 0 &mpic 63>; 232 marvell,pcie-port = <1>; 233 marvell,pcie-lane = <1>; 234 clocks = <&gateclk 10>; 235 status = "disabled"; 236 }; 237 238 pcie@7,0 { 239 device_type = "pci"; 240 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; 241 reg = <0x3800 0 0 0 0>; 242 #address-cells = <3>; 243 #size-cells = <2>; 244 #interrupt-cells = <1>; 245 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 246 0x81000000 0 0 0x81000000 0x7 0 1 0>; 247 interrupt-map-mask = <0 0 0 0>; 248 interrupt-map = <0 0 0 0 &mpic 64>; 249 marvell,pcie-port = <1>; 250 marvell,pcie-lane = <2>; 251 clocks = <&gateclk 11>; 252 status = "disabled"; 253 }; 254 255 pcie@8,0 { 256 device_type = "pci"; 257 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; 258 reg = <0x4000 0 0 0 0>; 259 #address-cells = <3>; 260 #size-cells = <2>; 261 #interrupt-cells = <1>; 262 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 263 0x81000000 0 0 0x81000000 0x8 0 1 0>; 264 interrupt-map-mask = <0 0 0 0>; 265 interrupt-map = <0 0 0 0 &mpic 65>; 266 marvell,pcie-port = <1>; 267 marvell,pcie-lane = <3>; 268 clocks = <&gateclk 12>; 269 status = "disabled"; 270 }; 271 272 pcie@9,0 { 273 device_type = "pci"; 274 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; 275 reg = <0x4800 0 0 0 0>; 276 #address-cells = <3>; 277 #size-cells = <2>; 278 #interrupt-cells = <1>; 279 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 280 0x81000000 0 0 0x81000000 0x9 0 1 0>; 281 interrupt-map-mask = <0 0 0 0>; 282 interrupt-map = <0 0 0 0 &mpic 99>; 283 marvell,pcie-port = <2>; 284 marvell,pcie-lane = <0>; 285 clocks = <&gateclk 26>; 286 status = "disabled"; 287 }; 288 289 pcie@10,0 { 290 device_type = "pci"; 291 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; 292 reg = <0x5000 0 0 0 0>; 293 #address-cells = <3>; 294 #size-cells = <2>; 295 #interrupt-cells = <1>; 296 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 297 0x81000000 0 0 0x81000000 0xa 0 1 0>; 298 interrupt-map-mask = <0 0 0 0>; 299 interrupt-map = <0 0 0 0 &mpic 103>; 300 marvell,pcie-port = <3>; 301 marvell,pcie-lane = <0>; 302 clocks = <&gateclk 27>; 303 status = "disabled"; 304 }; 305}; 306