xref: /linux/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml (revision 3a38ef2b3cb6b63c105247b5ea4a9cf600e673f0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PCIe Root Port Bridge Controller
8
9maintainers:
10  - Daire McNamara <daire.mcnamara@microchip.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-bus.yaml#
14  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
15
16properties:
17  compatible:
18    const: microchip,pcie-host-1.0 # PolarFire
19
20  reg:
21    maxItems: 2
22
23  reg-names:
24    items:
25      - const: cfg
26      - const: apb
27
28  clocks:
29    description:
30      Fabric Interface Controllers, FICs, are the interface between the FPGA
31      fabric and the core complex on PolarFire SoC. The FICs require two clocks,
32      one from each side of the interface. The "FIC clocks" described by this
33      property are on the core complex side & communication through a FIC is not
34      possible unless it's corresponding clock is enabled. A clock must be
35      enabled for each of the interfaces the root port is connected through.
36      This could in theory be all 4 interfaces, one interface or any combination
37      in between.
38    minItems: 1
39    items:
40      - description: FIC0's clock
41      - description: FIC1's clock
42      - description: FIC2's clock
43      - description: FIC3's clock
44
45  clock-names:
46    description:
47      As any FIC connection combination is possible, the names should match the
48      order in the clocks property and take the form "ficN" where N is a number
49      0-3
50    minItems: 1
51    maxItems: 4
52    items:
53      pattern: '^fic[0-3]$'
54
55  interrupts:
56    minItems: 1
57    items:
58      - description: PCIe host controller
59      - description: builtin MSI controller
60
61  interrupt-names:
62    minItems: 1
63    items:
64      - const: pcie
65      - const: msi
66
67  ranges:
68    maxItems: 1
69
70  dma-ranges:
71    minItems: 1
72    maxItems: 6
73
74  msi-controller:
75    description: Identifies the node as an MSI controller.
76
77  msi-parent:
78    description: MSI controller the device is capable of using.
79
80  interrupt-controller:
81    type: object
82    properties:
83      '#address-cells':
84        const: 0
85
86      '#interrupt-cells':
87        const: 1
88
89      interrupt-controller: true
90
91    required:
92      - '#address-cells'
93      - '#interrupt-cells'
94      - interrupt-controller
95
96    additionalProperties: false
97
98required:
99  - reg
100  - reg-names
101  - "#interrupt-cells"
102  - interrupts
103  - interrupt-map-mask
104  - interrupt-map
105  - msi-controller
106
107unevaluatedProperties: false
108
109examples:
110  - |
111    soc {
112            #address-cells = <2>;
113            #size-cells = <2>;
114            pcie0: pcie@2030000000 {
115                    compatible = "microchip,pcie-host-1.0";
116                    reg = <0x0 0x70000000 0x0 0x08000000>,
117                          <0x0 0x43000000 0x0 0x00010000>;
118                    reg-names = "cfg", "apb";
119                    device_type = "pci";
120                    #address-cells = <3>;
121                    #size-cells = <2>;
122                    #interrupt-cells = <1>;
123                    interrupts = <119>;
124                    interrupt-map-mask = <0x0 0x0 0x0 0x7>;
125                    interrupt-map = <0 0 0 1 &pcie_intc0 0>,
126                                    <0 0 0 2 &pcie_intc0 1>,
127                                    <0 0 0 3 &pcie_intc0 2>,
128                                    <0 0 0 4 &pcie_intc0 3>;
129                    interrupt-parent = <&plic0>;
130                    msi-parent = <&pcie0>;
131                    msi-controller;
132                    bus-range = <0x00 0x7f>;
133                    ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
134                    pcie_intc0: interrupt-controller {
135                        #address-cells = <0>;
136                        #interrupt-cells = <1>;
137                        interrupt-controller;
138                    };
139            };
140    };
141