xref: /linux/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml (revision 2eff01ee2881becc9daaa0d53477ec202136b1f4) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PCIe Root Port Bridge Controller
8
9maintainers:
10  - Daire McNamara <daire.mcnamara@microchip.com>
11
12allOf:
13  - $ref: plda,xpressrich3-axi-common.yaml#
14  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
15
16properties:
17  compatible:
18    const: microchip,pcie-host-1.0 # PolarFire
19
20  reg:
21    minItems: 3
22
23  reg-names:
24    minItems: 3
25
26  clocks:
27    description:
28      Fabric Interface Controllers, FICs, are the interface between the FPGA
29      fabric and the core complex on PolarFire SoC. The FICs require two clocks,
30      one from each side of the interface. The "FIC clocks" described by this
31      property are on the core complex side & communication through a FIC is not
32      possible unless it's corresponding clock is enabled. A clock must be
33      enabled for each of the interfaces the root port is connected through.
34      This could in theory be all 4 interfaces, one interface or any combination
35      in between.
36    minItems: 1
37    items:
38      - description: FIC0's clock
39      - description: FIC1's clock
40      - description: FIC2's clock
41      - description: FIC3's clock
42
43  clock-names:
44    description:
45      As any FIC connection combination is possible, the names should match the
46      order in the clocks property and take the form "ficN" where N is a number
47      0-3
48    minItems: 1
49    maxItems: 4
50    items:
51      pattern: '^fic[0-3]$'
52
53  ranges:
54    minItems: 1
55    maxItems: 3
56
57  dma-ranges:
58    minItems: 1
59    maxItems: 6
60
61unevaluatedProperties: false
62
63examples:
64  - |
65    soc {
66            #address-cells = <2>;
67            #size-cells = <2>;
68            pcie0: pcie@2030000000 {
69                    compatible = "microchip,pcie-host-1.0";
70                    reg = <0x0 0x70000000 0x0 0x08000000>,
71                          <0x0 0x43008000 0x0 0x00002000>,
72                          <0x0 0x4300a000 0x0 0x00002000>;
73                    reg-names = "cfg", "bridge", "ctrl";
74                    device_type = "pci";
75                    #address-cells = <3>;
76                    #size-cells = <2>;
77                    #interrupt-cells = <1>;
78                    interrupts = <119>;
79                    interrupt-map-mask = <0x0 0x0 0x0 0x7>;
80                    interrupt-map = <0 0 0 1 &pcie_intc0 0>,
81                                    <0 0 0 2 &pcie_intc0 1>,
82                                    <0 0 0 3 &pcie_intc0 2>,
83                                    <0 0 0 4 &pcie_intc0 3>;
84                    interrupt-parent = <&plic0>;
85                    msi-parent = <&pcie0>;
86                    msi-controller;
87                    bus-range = <0x00 0x7f>;
88                    ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
89                    pcie_intc0: interrupt-controller {
90                        #address-cells = <0>;
91                        #interrupt-cells = <1>;
92                        interrupt-controller;
93                    };
94            };
95    };
96