xref: /linux/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml (revision 001821b0e79716c4e17c71d8e053a23599a7a508) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PCIe Root Port Bridge Controller
8
9maintainers:
10  - Daire McNamara <daire.mcnamara@microchip.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-host-bridge.yaml#
14  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
15
16properties:
17  compatible:
18    const: microchip,pcie-host-1.0 # PolarFire
19
20  reg:
21    maxItems: 2
22
23  reg-names:
24    items:
25      - const: cfg
26      - const: apb
27
28  clocks:
29    description:
30      Fabric Interface Controllers, FICs, are the interface between the FPGA
31      fabric and the core complex on PolarFire SoC. The FICs require two clocks,
32      one from each side of the interface. The "FIC clocks" described by this
33      property are on the core complex side & communication through a FIC is not
34      possible unless it's corresponding clock is enabled. A clock must be
35      enabled for each of the interfaces the root port is connected through.
36      This could in theory be all 4 interfaces, one interface or any combination
37      in between.
38    minItems: 1
39    items:
40      - description: FIC0's clock
41      - description: FIC1's clock
42      - description: FIC2's clock
43      - description: FIC3's clock
44
45  clock-names:
46    description:
47      As any FIC connection combination is possible, the names should match the
48      order in the clocks property and take the form "ficN" where N is a number
49      0-3
50    minItems: 1
51    maxItems: 4
52    items:
53      pattern: '^fic[0-3]$'
54
55  interrupts:
56    minItems: 1
57    items:
58      - description: PCIe host controller
59      - description: builtin MSI controller
60
61  interrupt-names:
62    minItems: 1
63    items:
64      - const: pcie
65      - const: msi
66
67  ranges:
68    minItems: 1
69    maxItems: 3
70
71  dma-ranges:
72    minItems: 1
73    maxItems: 6
74
75  msi-controller:
76    description: Identifies the node as an MSI controller.
77
78  msi-parent:
79    description: MSI controller the device is capable of using.
80
81  interrupt-controller:
82    type: object
83    properties:
84      '#address-cells':
85        const: 0
86
87      '#interrupt-cells':
88        const: 1
89
90      interrupt-controller: true
91
92    required:
93      - '#address-cells'
94      - '#interrupt-cells'
95      - interrupt-controller
96
97    additionalProperties: false
98
99required:
100  - reg
101  - reg-names
102  - "#interrupt-cells"
103  - interrupts
104  - interrupt-map-mask
105  - interrupt-map
106  - msi-controller
107
108unevaluatedProperties: false
109
110examples:
111  - |
112    soc {
113            #address-cells = <2>;
114            #size-cells = <2>;
115            pcie0: pcie@2030000000 {
116                    compatible = "microchip,pcie-host-1.0";
117                    reg = <0x0 0x70000000 0x0 0x08000000>,
118                          <0x0 0x43000000 0x0 0x00010000>;
119                    reg-names = "cfg", "apb";
120                    device_type = "pci";
121                    #address-cells = <3>;
122                    #size-cells = <2>;
123                    #interrupt-cells = <1>;
124                    interrupts = <119>;
125                    interrupt-map-mask = <0x0 0x0 0x0 0x7>;
126                    interrupt-map = <0 0 0 1 &pcie_intc0 0>,
127                                    <0 0 0 2 &pcie_intc0 1>,
128                                    <0 0 0 3 &pcie_intc0 2>,
129                                    <0 0 0 4 &pcie_intc0 3>;
130                    interrupt-parent = <&plic0>;
131                    msi-parent = <&pcie0>;
132                    msi-controller;
133                    bus-range = <0x00 0x7f>;
134                    ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
135                    pcie_intc0: interrupt-controller {
136                        #address-cells = <0>;
137                        #interrupt-cells = <1>;
138                        interrupt-controller;
139                    };
140            };
141    };
142