1MediaTek Gen2 PCIe controller 2 3Required properties: 4- compatible: Should contain one of the following strings: 5 "mediatek,mt2701-pcie" 6 "mediatek,mt2712-pcie" 7 "mediatek,mt7622-pcie" 8 "mediatek,mt7623-pcie" 9- device_type: Must be "pci" 10- reg: Base addresses and lengths of the PCIe subsys and root ports. 11- reg-names: Names of the above areas to use during resource lookup. 12- #address-cells: Address representation for root ports (must be 3) 13- #size-cells: Size representation for root ports (must be 2) 14- clocks: Must contain an entry for each entry in clock-names. 15 See ../clocks/clock-bindings.txt for details. 16- clock-names: 17 Mandatory entries: 18 - sys_ckN :transaction layer and data link layer clock 19 Required entries for MT2701/MT7623: 20 - free_ck :for reference clock of PCIe subsys 21 Required entries for MT2712/MT7622: 22 - ahb_ckN :AHB slave interface operating clock for CSR access and RC 23 initiated MMIO access 24 Required entries for MT7622: 25 - axi_ckN :application layer MMIO channel operating clock 26 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when 27 pcie_mac_ck/pcie_pipe_ck is turned off 28 - obff_ckN :OBFF functional block operating clock 29 - pipe_ckN :LTSSM and PHY/MAC layer operating clock 30 where N starting from 0 to one less than the number of root ports. 31- phys: List of PHY specifiers (used by generic PHY framework). 32- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the 33 number of PHYs as specified in *phys* property. 34- power-domains: A phandle and power domain specifier pair to the power domain 35 which is responsible for collapsing and restoring power to the peripheral. 36- bus-range: Range of bus numbers associated with this controller. 37- ranges: Ranges for the PCI memory and I/O regions. 38 39Required properties for MT7623/MT2701: 40- #interrupt-cells: Size representation for interrupts (must be 1) 41- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 42 Please refer to the standard PCI bus binding document for a more detailed 43 explanation. 44- resets: Must contain an entry for each entry in reset-names. 45 See ../reset/reset.txt for details. 46- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the 47 number of root ports. 48 49Required properties for MT2712/MT7622: 50-interrupts: A list of interrupt outputs of the controller, must have one 51 entry for each PCIe port 52 53In addition, the device tree node must have sub-nodes describing each 54PCIe port interface, having the following mandatory properties: 55 56Required properties: 57- device_type: Must be "pci" 58- reg: Only the first four bytes are used to refer to the correct bus number 59 and device number. 60- #address-cells: Must be 3 61- #size-cells: Must be 2 62- #interrupt-cells: Must be 1 63- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 64 Please refer to the standard PCI bus binding document for a more detailed 65 explanation. 66- ranges: Sub-ranges distributed from the PCIe controller node. An empty 67 property is sufficient. 68 69Examples for MT7623: 70 71 hifsys: syscon@1a000000 { 72 compatible = "mediatek,mt7623-hifsys", 73 "mediatek,mt2701-hifsys", 74 "syscon"; 75 reg = <0 0x1a000000 0 0x1000>; 76 #clock-cells = <1>; 77 #reset-cells = <1>; 78 }; 79 80 pcie: pcie@1a140000 { 81 compatible = "mediatek,mt7623-pcie"; 82 device_type = "pci"; 83 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ 84 <0 0x1a142000 0 0x1000>, /* Port0 registers */ 85 <0 0x1a143000 0 0x1000>, /* Port1 registers */ 86 <0 0x1a144000 0 0x1000>; /* Port2 registers */ 87 reg-names = "subsys", "port0", "port1", "port2"; 88 #address-cells = <3>; 89 #size-cells = <2>; 90 #interrupt-cells = <1>; 91 interrupt-map-mask = <0xf800 0 0 0>; 92 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, 93 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, 94 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 95 clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 96 <&hifsys CLK_HIFSYS_PCIE0>, 97 <&hifsys CLK_HIFSYS_PCIE1>, 98 <&hifsys CLK_HIFSYS_PCIE2>; 99 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; 100 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, 101 <&hifsys MT2701_HIFSYS_PCIE1_RST>, 102 <&hifsys MT2701_HIFSYS_PCIE2_RST>; 103 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; 104 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, 105 <&pcie2_phy PHY_TYPE_PCIE>; 106 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; 107 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 108 bus-range = <0x00 0xff>; 109 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ 110 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ 111 112 pcie@0,0 { 113 reg = <0x0000 0 0 0 0>; 114 #address-cells = <3>; 115 #size-cells = <2>; 116 #interrupt-cells = <1>; 117 interrupt-map-mask = <0 0 0 0>; 118 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 119 ranges; 120 }; 121 122 pcie@1,0 { 123 reg = <0x0800 0 0 0 0>; 124 #address-cells = <3>; 125 #size-cells = <2>; 126 #interrupt-cells = <1>; 127 interrupt-map-mask = <0 0 0 0>; 128 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 129 ranges; 130 }; 131 132 pcie@2,0 { 133 reg = <0x1000 0 0 0 0>; 134 #address-cells = <3>; 135 #size-cells = <2>; 136 #interrupt-cells = <1>; 137 interrupt-map-mask = <0 0 0 0>; 138 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 139 ranges; 140 }; 141 }; 142 143Examples for MT2712: 144 145 pcie: pcie@11700000 { 146 compatible = "mediatek,mt2712-pcie"; 147 device_type = "pci"; 148 reg = <0 0x11700000 0 0x1000>, 149 <0 0x112ff000 0 0x1000>; 150 reg-names = "port0", "port1"; 151 #address-cells = <3>; 152 #size-cells = <2>; 153 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, 156 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, 157 <&pericfg CLK_PERI_PCIE0>, 158 <&pericfg CLK_PERI_PCIE1>; 159 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; 160 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; 161 phy-names = "pcie-phy0", "pcie-phy1"; 162 bus-range = <0x00 0xff>; 163 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 164 165 pcie0: pcie@0,0 { 166 reg = <0x0000 0 0 0 0>; 167 #address-cells = <3>; 168 #size-cells = <2>; 169 #interrupt-cells = <1>; 170 ranges; 171 interrupt-map-mask = <0 0 0 7>; 172 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 173 <0 0 0 2 &pcie_intc0 1>, 174 <0 0 0 3 &pcie_intc0 2>, 175 <0 0 0 4 &pcie_intc0 3>; 176 pcie_intc0: interrupt-controller { 177 interrupt-controller; 178 #address-cells = <0>; 179 #interrupt-cells = <1>; 180 }; 181 }; 182 183 pcie1: pcie@1,0 { 184 reg = <0x0800 0 0 0 0>; 185 #address-cells = <3>; 186 #size-cells = <2>; 187 #interrupt-cells = <1>; 188 ranges; 189 interrupt-map-mask = <0 0 0 7>; 190 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 191 <0 0 0 2 &pcie_intc1 1>, 192 <0 0 0 3 &pcie_intc1 2>, 193 <0 0 0 4 &pcie_intc1 3>; 194 pcie_intc1: interrupt-controller { 195 interrupt-controller; 196 #address-cells = <0>; 197 #interrupt-cells = <1>; 198 }; 199 }; 200 }; 201 202Examples for MT7622: 203 204 pcie: pcie@1a140000 { 205 compatible = "mediatek,mt7622-pcie"; 206 device_type = "pci"; 207 reg = <0 0x1a140000 0 0x1000>, 208 <0 0x1a143000 0 0x1000>, 209 <0 0x1a145000 0 0x1000>; 210 reg-names = "subsys", "port0", "port1"; 211 #address-cells = <3>; 212 #size-cells = <2>; 213 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>, 214 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 215 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, 216 <&pciesys CLK_PCIE_P1_MAC_EN>, 217 <&pciesys CLK_PCIE_P0_AHB_EN>, 218 <&pciesys CLK_PCIE_P1_AHB_EN>, 219 <&pciesys CLK_PCIE_P0_AUX_EN>, 220 <&pciesys CLK_PCIE_P1_AUX_EN>, 221 <&pciesys CLK_PCIE_P0_AXI_EN>, 222 <&pciesys CLK_PCIE_P1_AXI_EN>, 223 <&pciesys CLK_PCIE_P0_OBFF_EN>, 224 <&pciesys CLK_PCIE_P1_OBFF_EN>, 225 <&pciesys CLK_PCIE_P0_PIPE_EN>, 226 <&pciesys CLK_PCIE_P1_PIPE_EN>; 227 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", 228 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", 229 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; 230 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; 231 phy-names = "pcie-phy0", "pcie-phy1"; 232 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 233 bus-range = <0x00 0xff>; 234 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 235 236 pcie0: pcie@0,0 { 237 reg = <0x0000 0 0 0 0>; 238 #address-cells = <3>; 239 #size-cells = <2>; 240 #interrupt-cells = <1>; 241 ranges; 242 interrupt-map-mask = <0 0 0 7>; 243 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 244 <0 0 0 2 &pcie_intc0 1>, 245 <0 0 0 3 &pcie_intc0 2>, 246 <0 0 0 4 &pcie_intc0 3>; 247 pcie_intc0: interrupt-controller { 248 interrupt-controller; 249 #address-cells = <0>; 250 #interrupt-cells = <1>; 251 }; 252 }; 253 254 pcie1: pcie@1,0 { 255 reg = <0x0800 0 0 0 0>; 256 #address-cells = <3>; 257 #size-cells = <2>; 258 #interrupt-cells = <1>; 259 ranges; 260 interrupt-map-mask = <0 0 0 7>; 261 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 262 <0 0 0 2 &pcie_intc1 1>, 263 <0 0 0 3 &pcie_intc1 2>, 264 <0 0 0 4 &pcie_intc1 3>; 265 pcie_intc1: interrupt-controller { 266 interrupt-controller; 267 #address-cells = <0>; 268 #interrupt-cells = <1>; 269 }; 270 }; 271 }; 272