xref: /linux/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml (revision ff124bbbca1d3a07fa1392ffdbbdeece71f68ece) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Gen3 PCIe controller on MediaTek SoCs
8
9maintainers:
10  - Jianjun Wang <jianjun.wang@mediatek.com>
11
12description: |+
13  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14  and compatible with Gen2, Gen1 speed.
15
16  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
17  block diagram is as follows:
18
19                    +-----+
20                    | GIC |
21                    +-----+
22                       ^
23                       |
24                   port->irq
25                       |
26               +-+-+-+-+-+-+-+-+
27               |0|1|2|3|4|5|6|7| (PCIe intc)
28               +-+-+-+-+-+-+-+-+
29                ^ ^           ^
30                | |    ...    |
31        +-------+ +------+    +-----------+
32        |                |                |
33  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
34  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
35  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
36   ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
37   | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
38   | |      |  |    | |      |  |    | |      |  |
39
40    (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
41
42  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43  each set has its own address for MSI message, and supports 32 MSI vectors
44  to generate interrupt.
45
46properties:
47  compatible:
48    oneOf:
49      - items:
50          - enum:
51              - mediatek,mt7981-pcie
52              - mediatek,mt7986-pcie
53              - mediatek,mt8188-pcie
54              - mediatek,mt8195-pcie
55          - const: mediatek,mt8192-pcie
56      - items:
57          - enum:
58              - mediatek,mt6991-pcie
59          - const: mediatek,mt8196-pcie
60      - const: mediatek,mt8192-pcie
61      - const: mediatek,mt8196-pcie
62      - const: airoha,en7581-pcie
63
64  reg:
65    maxItems: 1
66
67  reg-names:
68    items:
69      - const: pcie-mac
70
71  interrupts:
72    maxItems: 1
73
74  ranges:
75    minItems: 1
76    maxItems: 8
77
78  iommu-map:
79    maxItems: 1
80
81  iommu-map-mask:
82    const: 0
83
84  resets:
85    minItems: 1
86    maxItems: 3
87
88  reset-names:
89    minItems: 1
90    maxItems: 3
91    items:
92      enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
93
94  clocks:
95    minItems: 1
96    maxItems: 6
97
98  clock-names:
99    minItems: 1
100    maxItems: 6
101
102  assigned-clocks:
103    maxItems: 1
104
105  assigned-clock-parents:
106    maxItems: 1
107
108  phys:
109    maxItems: 1
110
111  phy-names:
112    items:
113      - const: pcie-phy
114
115  power-domains:
116    maxItems: 1
117
118  mediatek,pbus-csr:
119    $ref: /schemas/types.yaml#/definitions/phandle-array
120    items:
121      - items:
122          - description: phandle to pbus-csr syscon
123          - description: offset of pbus-csr base address register
124          - description: offset of pbus-csr base address mask register
125    description:
126      Phandle with two arguments to the syscon node used to detect if
127      a given address is accessible on PCIe controller.
128
129  '#interrupt-cells':
130    const: 1
131
132  interrupt-controller:
133    description: Interrupt controller node for handling legacy PCI interrupts.
134    type: object
135    properties:
136      '#address-cells':
137        const: 0
138      '#interrupt-cells':
139        const: 1
140      interrupt-controller: true
141
142    required:
143      - '#address-cells'
144      - '#interrupt-cells'
145      - interrupt-controller
146
147    additionalProperties: false
148
149required:
150  - compatible
151  - reg
152  - reg-names
153  - interrupts
154  - ranges
155  - clocks
156  - clock-names
157  - '#interrupt-cells'
158  - interrupt-controller
159
160allOf:
161  - $ref: /schemas/pci/pci-host-bridge.yaml#
162  - if:
163      properties:
164        compatible:
165          const: mediatek,mt8192-pcie
166    then:
167      properties:
168        clocks:
169          minItems: 6
170
171        clock-names:
172          items:
173            - const: pl_250m
174            - const: tl_26m
175            - const: tl_96m
176            - const: tl_32k
177            - const: peri_26m
178            - const: top_133m
179
180        resets:
181          minItems: 1
182          maxItems: 2
183
184        reset-names:
185          minItems: 1
186          maxItems: 2
187
188        mediatek,pbus-csr: false
189
190  - if:
191      properties:
192        compatible:
193          contains:
194            enum:
195              - mediatek,mt8188-pcie
196              - mediatek,mt8195-pcie
197    then:
198      properties:
199        clocks:
200          minItems: 6
201
202        clock-names:
203          items:
204            - const: pl_250m
205            - const: tl_26m
206            - const: tl_96m
207            - const: tl_32k
208            - const: peri_26m
209            - const: peri_mem
210
211        resets:
212          minItems: 1
213          maxItems: 2
214
215        reset-names:
216          minItems: 1
217          maxItems: 2
218
219        mediatek,pbus-csr: false
220
221  - if:
222      properties:
223        compatible:
224          contains:
225            enum:
226              - mediatek,mt8196-pcie
227    then:
228      properties:
229        clocks:
230          minItems: 6
231
232        clock-names:
233          items:
234            - const: pl_250m
235            - const: tl_26m
236            - const: bus
237            - const: low_power
238            - const: peri_26m
239            - const: peri_mem
240
241        resets:
242          minItems: 2
243
244        reset-names:
245          items:
246            - const: phy
247            - const: mac
248
249        mediatek,pbus-csr: false
250
251  - if:
252      properties:
253        compatible:
254          contains:
255            enum:
256              - mediatek,mt7986-pcie
257    then:
258      properties:
259        clocks:
260          minItems: 4
261          maxItems: 4
262
263        clock-names:
264          items:
265            - const: pl_250m
266            - const: tl_26m
267            - const: peri_26m
268            - const: top_133m
269
270        resets:
271          minItems: 1
272          maxItems: 2
273
274        reset-names:
275          minItems: 1
276          maxItems: 2
277
278        mediatek,pbus-csr: false
279
280  - if:
281      properties:
282        compatible:
283          const: airoha,en7581-pcie
284    then:
285      properties:
286        clocks:
287          maxItems: 1
288
289        clock-names:
290          items:
291            - const: sys-ck
292
293        resets:
294          minItems: 3
295
296        reset-names:
297          items:
298            - const: phy-lane0
299            - const: phy-lane1
300            - const: phy-lane2
301
302unevaluatedProperties: false
303
304examples:
305  - |
306    #include <dt-bindings/interrupt-controller/arm-gic.h>
307    #include <dt-bindings/interrupt-controller/irq.h>
308
309    bus {
310        #address-cells = <2>;
311        #size-cells = <2>;
312
313        pcie: pcie@11230000 {
314            compatible = "mediatek,mt8192-pcie";
315            device_type = "pci";
316            #address-cells = <3>;
317            #size-cells = <2>;
318            reg = <0x00 0x11230000 0x00 0x4000>;
319            reg-names = "pcie-mac";
320            interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
321            bus-range = <0x00 0xff>;
322            ranges = <0x82000000 0x00 0x12000000 0x00
323                      0x12000000 0x00 0x1000000>;
324            clocks = <&infracfg 44>,
325                     <&infracfg 40>,
326                     <&infracfg 43>,
327                     <&infracfg 97>,
328                     <&infracfg 99>,
329                     <&infracfg 111>;
330            clock-names = "pl_250m", "tl_26m", "tl_96m",
331                          "tl_32k", "peri_26m", "top_133m";
332            assigned-clocks = <&topckgen 50>;
333            assigned-clock-parents = <&topckgen 91>;
334
335            phys = <&pciephy>;
336            phy-names = "pcie-phy";
337
338            resets = <&infracfg_rst 2>,
339                     <&infracfg_rst 3>;
340            reset-names = "phy", "mac";
341
342            #interrupt-cells = <1>;
343            interrupt-map-mask = <0 0 0 0x7>;
344            interrupt-map = <0 0 0 1 &pcie_intc 0>,
345                            <0 0 0 2 &pcie_intc 1>,
346                            <0 0 0 3 &pcie_intc 2>,
347                            <0 0 0 4 &pcie_intc 3>;
348            pcie_intc: interrupt-controller {
349                      #address-cells = <0>;
350                      #interrupt-cells = <1>;
351                      interrupt-controller;
352            };
353        };
354    };
355